VS1003 Datasheet - VLSI

1 VS1003VS1003 - MP3/WMA AUDIO CODECF eatures Decodes MPEG 1 & 2 audio layer III(CBR +VBR +ABR); WMA profiles (5-384kbit/s); WAV (PCM +IMA ADPCM); General MIDI / SP-MIDI files Encodes IMA ADPCM from microphoneor line input Streaming support for MP3 and WAV Bass and treble controls Operates with a single MHz clock Internal PLL clock multiplier Low-power operation High-quality on-chip stereo DAC with nophase error between channels Stereo earphone driver capable of driv-ing a 30 load Separate operating voltages for analog,digital and I/O KiB On-chip RAM for user code /data Serial control and data interfaces Can be used as a slave co-processor SPI flash boot for special applications UART for debugging purposes New functions may be added with soft-ware and 4 GPIO pinsInstruction RAMI nstruction ROMS tereo DACMonoADCLRUARTS erialData/ControlInterfaceStereo Ear phone DriverDREQSOSISCLKXCSRXTX audiooutputX ROMX RAMY ROMY RAM4 GPIOGPIOVSDSP4 XDCSVS1003 MIC AMP ClockmultiplierMUXlineaudiomicaudioDescr iptionVS1003 is a single-chip MP3/WMA/MIDI au-dio decoder and ADPCM encoder.

2 It containsa high-performance, proprietary low-power DSPprocessor core VS_DSP4, working data mem-ory, 5 KiB instruction RAM and KiB dataRAM for user applications, serial control andinput data interfaces, 4 general purpose I/Opins, an UART, as well as a high-quality variable-sample-rate mono ADC and stereo DAC, fol-lowed by an earphone amplifier and a com-mon receives its input bitstream througha serial input bus, which it listens to as asystem slave. The input stream is decodedand passed through a digital volume controlto an 18-bit oversampling, multi-bit, sigma-delta DAC. The decoding is controlled via aserial control bus. In addition to the basic de-coding, it is possible to add application spe-cific features, like DSP effects, to the userRAM : , 2018-03-161VS1003 CONTENTSC ontentsVS10031 Table of Contents2 List of Figures51 Licenses62 Disclaimer63 Definitions64 Characteristics & Maximum Ratings.

3 Operating Conditions .. Characteristics .. Consumption .. Characteristics .. Characteristics - Boot Initialization .. characteristics .. input ADC .. input ADC .. and LEFT outputs .. 115 Packages and Pin .. and BGA-49 Pin Descriptions .. 136 Connection Diagram, LQFP-48157 SPI .. Bus Pin Descriptions .. Native Modes (New Mode) .. Compatibility Mode .. Request Pin DREQ .. Protocol for Serial Data Interface (SDI) .. in VS10xx Native Modes (New Mode, recommended) .. in VS1001 Compatibility Mode .. SDI Mode .. Protocol for Serial Command Interface (SCI) .. Read .. Write.

4 Timing Diagram .. Examples with SM_SDINEW and SM_SDISHARED set .. SCI Writes .. 21 Version: , SDI Bytes .. Operation in Middle of Two SDI Bytes .. 228 Functional Features .. Audio Codecs .. MP3 (MPEG layer III) Formats .. WMA Formats .. RIFF WAV Formats .. MIDI Formats .. Flow of VS1003 .. Data Interface (SDI) .. Control Interface (SCI) .. Registers .. (RW) .. (RW) .. (RW) .. (RW) .. (RW) .. (RW) .. (RW) .. (W) .. and SCI_HDAT1 (R) .. SCI_AIADDR (RW) .. SCI_VOL (RW) .. SCI_AICTRL[x] (RW) .. 369 .. Reset .. Reset.

5 Recording .. ADPCM mode .. IMA ADPCM Data .. a RIFF Header .. ADPCM Data .. Rate Considerations .. Code .. Boot .. PCM data .. Tests .. Test .. Test .. Test .. Test .. 4410 VS1003 Who Needs to Read This Chapter .. The Processor Core .. VS1003 Memory Map .. 45 Version: , SCI Registers .. Serial Data Registers .. DAC Registers .. GPIO Registers .. Interrupt Registers .. A/D Modulator Registers .. Watchdog .. Registers .. UART (Universal Asynchronous Receiver/Transmitter) .. Registers .. Status UARTx_STATUS.

6 Data UARTx_DATA .. Data High UARTx_DATAH .. Divider UARTx_DIV .. Interrupts and Operation .. Timers .. Registers .. Configuration TIMER_CONFIG .. Configuration TIMER_ENABLE .. Timer X Startvalue TIMER_Tx[L/H] .. Timer X Counter TIMER_TxCNT[L/H] .. Interrupts .. System Vector Tags .. AudioInt, 0x20 .. SciInt, 0x21 .. DataInt, 0x22 .. ModuInt, 0x23 .. TxInt, 0x24 .. RxInt, 0x25 .. Timer0 Int, 0x26 .. Timer1 Int, 0x27 .. UserCodec, 0x0 .. System Vector Functions .. WriteIRam(), 0x2 .. ReadIRam(), 0x4 .. DataBytes(), 0x6 .. GetDataByte(), 0x8.

7 GetDataWords(), 0xa .. Reboot(), 0xc .. 5911 Latest Document Version Changes6012 Contact Information61 Version: , 2018-03-164VS1003 LIST OF FIGURESList of Figures1 Measured ADC performance of the LINEIN pin.. 102 Measured ADC performance of the MIC pins (differential).. 103 Measured performance of RIGHT (or LEFT) output.. 114 Typical spectrum of RIGHT (or LEFT) output.. 115 Pin Configuration, LQFP-48.. 126 Pin Configuration, BGA-49.. 127 Typical Connection Diagram Using LQFP-48.. 158 BSYNC Signal - one byte transfer.. 189 BSYNC Signal - two byte transfer.. 1810 SCI Word Read .. 1911 SCI Word Write .. 1912 SPI Timing Diagram.. 2013 Two SCI Operations.

8 2114 Two SDI Bytes.. 2115 Two SDI Bytes Separated By an SCI Operation.. 2216 Data Flow of VS1003 .. 2717 ADPCM Frequency Responses with 8kHz sample rate.. 3018 User s Memory Map.. 4619RS232 Serial Interface Protocol .. 51 Version: , 2018-03-165VS10033 DEFINITIONS1 LicensesVS1003 contains WMA decoding technology from product is protected by certain intellectual property rights of Microsoft and cannotbe used or further distributed without a license from DisclaimerAll properties and figures are subject to DefinitionsABRA verage BitRate. Bitrate of stream may vary locally, but will stay close to a given numberwhen averaged over a longer , 8 BitRate. Bitrate of stream will be the same for each compression Common Buffer.

9 Outputs DC as Kibi =210= 1024 (IEC 60027-2).Mi Mebi =220= 1048576 (IEC 60027-2).SCIS erial Control Interface, an SPI bus for VS1003 Data Interface, an SPI bus for VS1003 bitstream BitRate. Bitrate will vary depending on the complexity of the source Solution s DSP Solution s Integrated Development In VS_DSP, instruction words are 32 bits and data words are 16 bits : , 2018-03-166VS10034 CHARACTERISTICS & SPECIFICATIONS4 Characteristics & Absolute Maximum RatingsParameterSymbolMinMaxUnitAnalog Positive Positive Positive at Any Digital Output 50mAVoltage at Any Digital + Temperature-40+85 CStorage Temperature-65+150 C1 Must not exceed Recommended Operating ConditionsParameterSymbolMinTypMaxUnitAm bient Operating Temperature-40+85 CAnalog and Digital Ground1 AGND Clock Clock Clock 4 Master Clock Duty Cycle405060%1 Must be connected together as close the device as possible for latch-up maximum sample rate that can be played with correct speed is.

10 XTALI must be at least MHz to be able to play 48 kHz at correct value . Recommended SC_MULT= , SC_ADD= (SCI_CLOCKF=0x9000). MHz is the maximum clock for the full CVDD range.( MHz MHz)Version: , 2018-03-167VS10034 CHARACTERISTICS & Analog CharacteristicsUnless otherwise noted:AVDD= ,CVDD= ,IOVDD= , TA= +70 C,XTALI= , DAC tested with Hz full-scale output sinewave, measurementbandwidth Hz, analog output load: LEFT to GBUF 30 , RIGHT to GBUF 30 . Mi-crophone test amplitude 50 mVpp, f=1 kHz, Line input test amplitude Vpp, f=1 Resolution18bitsTotal Harmonic Range (DAC unmuted, A-weighted)IDR>90dBS/N Ratio (full scale signal)SNR705834dBInterchannel Isolation (Cross Talk)5075dBInterchannel Isolation (Cross Talk), with GBUF40dBInterchannel Gain Scale Output Voltage (Peak-to-peak)