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Wireless SoC Family Data Sheet - Silicon Labs

EFR32MG21 Mighty Gecko MultiprotocolWireless SoC Family Data SheetThe Mighty Gecko multiprotocol Family of SoCs is part of the Wire-less Gecko portfolio. Mighty Gecko SoCs are ideal for enabling en-ergy-friendly multiprotocol, multiband networking for IoT single-die solution combines an 80 MHz ARM Cortex-M33 with a high GHz radio to provide an industry-leading, energy efficient Wireless SoC for IoT con-nected Gecko applications include:KEY FEATURES 32-bit ARM Cortex -M33 core with 80 MHz maximum operating frequency Up to 1024 kB of flash and 96 kB of RAM 12-channel Peripheral Reflex Systemenabling autonomous interaction of MCUperipherals Integrated PA with up to 20 dBm ( ) TX power Robust peripheral set and up to 20 GPIOin a 4x4 QFN package IoT Multi-Protocol Devices Lighting Connected Home Gatew

For devices that support 20 dBm, these pins also interface to the 20 dBm on-chip balun. Integrated switches select either RF2G4_IO1 or RF2G4_IO2 to be the active path.

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Transcription of Wireless SoC Family Data Sheet - Silicon Labs

1 EFR32MG21 Mighty Gecko MultiprotocolWireless SoC Family Data SheetThe Mighty Gecko multiprotocol Family of SoCs is part of the Wire-less Gecko portfolio. Mighty Gecko SoCs are ideal for enabling en-ergy-friendly multiprotocol, multiband networking for IoT single-die solution combines an 80 MHz ARM Cortex-M33 with a high GHz radio to provide an industry-leading, energy efficient Wireless SoC for IoT con-nected Gecko applications include:KEY FEATURES 32-bit ARM Cortex -M33 core with 80 MHz maximum operating frequency Up to 1024 kB of flash and 96 kB of RAM 12-channel Peripheral Reflex Systemenabling autonomous interaction of MCUperipherals Integrated PA with up to 20 dBm ( )

2 TX power Robust peripheral set and up to 20 GPIOin a 4x4 QFN package IoT Multi-Protocol Devices Lighting Connected Home Gateways and Digital Assistants Building Automation and SecuritySecuritySecure Debug AuthenticationTimers and Triggers32-bit busPeripheral Reflex SystemSerial InterfacesI/O PortsAnalog I/FLowest power mode with peripheral operational:USARTI2 CExternal InterruptsGeneral Purpose I/OPin ResetPin WakeupIADCA nalog ComparatorEM4 ShutoffEnergy ManagementBrown-Out DetectorVoltage RegulatorPower-On ResetClock ManagementHF Crystal OscillatorLF Crystal OscillatorLFRC OscillatorHFRC OscillatorEM23 HF RC OscillatorCrypto AccelerationSecure ElementUltra LF RC OscillatorCore / MemoryARM CortexTM M33 processorwith DSP extensions.

3 FPU and Trust ZoneETMS ecure DebugRAM MemoryLDMA ControllerFlash Program MemoryReal Time Capture CounterTimer/CounterLow Energy TimerWatchdog TimerProtocol TimerEM3 StopEM2 Deep SleepEM1 SleepEM0 ActiveTrue Random Number GeneratorFast StartupRC OscillatorBack-Up Real Time CounterRadio TransceiverDEMODAGCIFADCCRCBUFCMODFRCRAC F requency SynthPGARF FrontendIQPALNAPAEUIS ecure Boot with Root of Trust and Secure LoaderDPA | Building a more connected 1. Feature ListThe EFR32MG21 highlighted features are listed below. Low Power Wireless System-on-Chip High Performance 32-bit 80 MHz ARM Cortex -M33 withDSP instruction and floating-point unit for efficient signalprocessing Up to 1024 kB flash program memory Up to 96 kB RAM data memory GHz radio operation TX power up to 20 dBm Low Energy Consumption mA RX current at GHz (1 Mbps GFSK) mA RX current at GHz (250 kbps O-QPSK DSSS) mA TX current @ 0 dBm output power at GHz mA TX current @ 10 dBm output power at GHz A/MHz in Active Mode (EM0)

4 A EM2 DeepSleep current(96 kB RAM retention and RTC running from LFXO) A EM2 DeepSleep current(16 kB RAM retention and RTC running from LFRCO) High Receiver Performance dBm sensitivity @ 250 kbps O-QPSK DSSS dBm sensitivity @ 1 Mbit/s GFSK dBm sensitivity @ 2 Mbit/s GFSK dBm sensitivity @ 125 kbps GFSK Supported Modulation Formats GFSK OQPSK Protocol Support Bluetooth Low Energy (Bluetooth 5) Zigbee Thread Wide selection of MCU peripherals 12-bit 1 Msps SAR Analog to Digital Converter (ADC) 2 Analog Comparator (ACMP) Up to 20 General Purpose I/O pins with output state reten-tion and asynchronous interrupts 8 Channel DMA Controller 12 Channel Peripheral Reflex System (PRS) 2 16-bit Timer/Counter 3 Compare/Capture/PWM channels 1 32-bit Timer/Counter 3 Compare/Capture/PWM channels 32-bit Real Time Counter 24-bit Low Energy Timer for waveform generation 2 Watchdog Timer 3 Universal Synchronous/Asynchronous Receiver/Trans-mitter (UART/SPI/SmartCard(ISO 7816)/IrDA/I2S)

5 2 I2C interface with SMBus support Wide Operating Range to V single power supply -40 to 125 C ambient Security Secure Boot with Root of Trust and Secure Loader (RTSL) Hardware Cryptographic Acceleration with DPA counter-measures for AES128/256, SHA-1, SHA-2 (up to 256-bit),ECC (up to 256-bit), ECDSA, ECDH and J-Pake True Random Number Generator (TRNG) compliant withNIST SP800-90 and AIS-31 ARM TrustZone Secure Debug with lock/unlock QFN32 4x4 mm Package mm pitchEFR32MG21 Mighty Gecko Multiprotocol Wireless SoC Family Data SheetFeature | Building a more connected | 22.

6 Ordering InformationTable Ordering InformationOrdering CodeProtocol StackMax TX Power @ Fre-quency BandFlash(kB)RAM(kB)SecurityGPIOPack-age EFR32MG21A010F1024IM32-B Zigbee Thread10 dBm @ GHz102496 Secure Ele-ment20 QFN32 EFR32MG21A010F512IM32-B Zigbee Thread10 dBm @ GHz51264 Secure Ele-ment20 QFN32 EFR32MG21A010F768IM32-B Zigbee Thread10 dBm @ GHz76864 Secure Ele-ment20 QFN32 EFR32MG21A020F1024IM32-B Zigbee Thread20 dBm @ GHz102496 Secure Ele-ment20 QFN32 EFR32MG21A020F512IM32-B Zigbee Thread20 dBm @ GHz51264 Secure Ele-ment20 QFN32 EFR32MG21A020F768IM32-B Zigbee Thread20 dBm @ GHz76864 Secure Ele-ment20 QFN32

7 EFR32MG21 Mighty Gecko Multiprotocol Wireless SoC Family Data SheetOrdering | Building a more connected | 3 Table of Contents1. Feature Ordering System Antenna Fractional-N Frequency Receiver Transmitter Packet and State Data Radio Controller (RAC).. General Purpose Input/Output (GPIO).. Clock Management Unit (CMU).. Internal and External Counters/Timers and Timer/Counter (TIMER).. Low Energy Timer (LETIMER).. Real Time Clock with Capture (RTCC).. Back-Up Real Time Watchdog Timer (WDOG).

8 Communications and Other Digital Universal Synchronous/Asynchronous Receiver/Transmitter (USART).. Inter-Integrated Circuit Interface (I2C) .. Peripheral Reflex System (PRS).. Security Secure Boot with Root of Trust and Secure Loader (RTSL).. Cryptographic True Random Number Secure Debug with Analog Comparator (ACMP).. Analog to Digital Converter (IADC).. Reset Management Unit (RMU).. Core and Processor Memory System Controller (MSC).. Linked Direct Memory Access Controller (LDMA).. Memory Configuration | Building a more connected | 44.

9 Electrical Electrical Absolute Maximum General Operating Thermal Current GHz RF Transceiver Flash Wake Up, Entry, and Exit GPIO Pins (3V GPIO pins).. Analog to Digital Converter (ADC).. Analog Comparator (ACMP).. Temperature Brown Out SPI Electrical I2C Electrical Typical Performance Supply GHz Typical Connection RF Matching GHz 0 dBm Matching GHz 10 dBm Matching GHz 20 dBm Matching Other Pin QFN32 Device Alternate Function Analog Peripheral Digital Peripheral QFN32 Package QFN32 Package QFN32 PCB Land QFN32 Package Revision | Building a more connected | 53.

10 System IntroductionThe EFR32 product Family combines an energy-friendly MCU with a high performance radio transceiver. The devices are well suited forsecure connected IoT multiprotocol devices requiring high performance and low energy consumption. This section gives a short intro-duction to the full radio and MCU system. The detailed functional description can be found in the EFR32xG21 Reference block diagram of the EFR32MG21 Family is shown in Figure Detailed EFR32MG21 Block Diagram on page 6. The diagramshows a superset of features available on the Family , which vary by OPN.


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