Working With Libraries 5 - VLSI IP

1 Compiler User Guide5 Working with Libraries5 This chapter contains the following sections: Selecting a Semiconductor Vendor Understanding the Library Requirements Specifying Libraries Loading Libraries Listing Libraries Reporting Library Contents Specifying Library Objects Directing Library Cell Usage Removing Libraries From Memory Saving Compiler User GuideSelecting a Semiconductor VendorOne of the first things you must do when designing a chip is to selectthe semiconductor vendor and technology you want to use. Considerthe following issues during the selection process: Maximum frequency of operation Physical restrictions Power restrictions Packaging restrictions Clock-tree implementation Floorplanning Back-annotation support Design support for Libraries , megacells, and RAMs Available cores Available test methods and scan stylesUnderstanding the Library RequirementsDesign Compiler uses these Libraries : Technology Libraries Symbol Libraries DesignWare Compiler User GuideThe following sections describe these LibrariesTechnology Libraries contain information about the characteristics andfunctions of each cell provided in a semiconductor vendor s vendors maintain and distribute the characteristics include information such as cell names, pinnames, area, delay times, and pin loading.

2 The technology libraryalso defines the conditions that must be met for a functional design(for example, the maximum transition time for nets). These conditionsare called design rule addition to cell information and design rule constraints, technologylibraries specify the operating conditions and wire load modelsspecific to that Compiler requires the technology Libraries to be in .db most cases, your semiconductor vendor provides you .db formatlibraries. If you are provided only with library source code, see theLibrary Compiler documentation for information about generatingtechnology Compiler uses technology Libraries to Implement the design functionThe technology Libraries that Design Compiler maps to duringoptimization are called target Libraries . The target Libraries containthe cells used to generate the netlist and definitions for thedesign s operating Compiler User GuideThe target Libraries used to compile or translate a design becomethe local link Libraries for the design.

3 Design Compiler saves thisinformation in the design slocal_link_libraryattribute. See Working with Attributes in Chapter 6 for information aboutattributes. Resolve cell referencesThe technology Libraries that Design Compiler uses to resolve cellreferences are called link Libraries . In addition to technologylibraries, link Libraries can also include design files. The linklibraries contain the descriptions of cells (library cells as well assubdesigns) in a mapped Libraries include both local link Libraries (local_link_library attribute) and system link Libraries (link_library variable).See Linking Designs in Chapter 6 for more information aboutresolving references. Calculate timing values and path delaysThe link Libraries define the delay models used to calculate timingvalues and path delays. See the Library Compiler documentationfor information about the various delay LibrariesSymbol Libraries contain definitions of the graphic symbols thatrepresent library cells in the design schematics.

4 Semiconductorvendors maintain and distribute the symbol Compiler User GuideDesign Compiler uses symbol Libraries to generate the designschematic. You must have Design Analyzer to view the you generate the design schematic, Design Compiler performsa one-to-one mapping of cells in the netlist to cells in the LibrariesA DesignWare library is a collection of reusable circuit-design buildingblocks (components) that are tightly integrated into the Synopsyssynthesis components that implement many of the built-in HDLoperators are provided by Synopsys. These operators include +, -, *,<, >, <=, >=, and the operations defined by if and case DesignWare Libraries can be developed by users at theirsites by using DesignWare Developer, or they can be licensed fromSynopsys or from third parties. To use licensed DesignWarecomponents, you need a license Compiler User GuideSpecifying LibrariesYou use dc_shell variables to specify the Libraries used by DesignCompiler.

5 Table 5-1 lists the variables for each library type as well asthe typical file extension for the a Library Search PathYou can specify the library location by using either the complete pathor only the file name. If you specify only the file name, Design Compileruses the search path defined in thesearch_pathvariable to locatethe library files. By default, the search path includes the currentworking directory and $SYNOPSYS/ Libraries /syn. Design Compilerlooks for the library files, starting with the leftmost directory specifiedin thesearch_pathvariable, and uses the first matching library fileit example, assume that you have technology Libraries in both the lib directory and the vhdl directory. Given thefollowing search path,search_path = {lib vhdl} + search_pathTable 5-1 Library VariablesLibrary TypeVariableDefault ValueFileExtensionTarget Librarytarget_library{ }.dbLink Librarylink_library{ * , }.dbSymbol Librarysymbol_library{ }.

6 SdbDesignWare Librarysynthetic_library,{}. Compiler User GuideDesign Compiler uses the file found in the lib directory,because it encounters the lib directory can use thewhich command to see which library file DesignCompiler finds (in order).dc_shell>which {"/usr/ ", "/usr/ "}Specifying Technology LibrariesSpecify the same value for the target library and the link library (exceptwhen performing technology translation). For the link library, youshould also specify the asterisk character (*), which specifies thatDesign Compiler should also search the designs in memory whenresolving cell references. If thelink_library variable has noasterisk, the designs loaded in memory are not searched. As a result,designs might not be found during linking and might specifying the files in thelink_library variable, considerthat Design Compiler searches these files from left to right whenresolving references and stops searching when it finds a the following example, the designs in memory are searched beforethe lsi_10k library:link_library = {"*" }See Linking Designs in Chapter 6 for more information aboutresolving Compiler User GuideSpecifying DesignWare LibrariesYou do not need to specify the standard synthetic library, , that implements the built-in HDL operators.

7 Thesoftware automatically uses this you are using additional DesignWare Libraries , you must specifythese Libraries , using thesynthetic_library variable (foroptimization purposes) and thelink_library variable (for cellresolution purposes).For more information about using DesignWare Libraries , see theDesignWare User LibrariesDesign Compiler uses binary Libraries (.db format for technologylibraries and .sdb format for symbol Libraries ), and automatically loadsthese Libraries when your library is not in the appropriate binary format, use theread_libcommand to compile the library source. Theread_libcommand requires a Library-Compiler manually load a binary library, use theread >read >read Compiler User GuideListing LibrariesDesign Compiler refers to a library loaded in memory by its library statement in the library source defines the library list the names of the Libraries loaded in memory, use thelist_libs >list_libsmy_lib my_symbol_lib1To list the path and file name information along with the names, usethelist - Libraries command (dcsh mode only).

8 Dc_shell>list -librariesLibrary File Path------- ---- ----my_lib /synopsys/librariesmy_symbol_lib /synopsys/librariesReporting Library ContentsUse thereport_lib command to report the contents of a command can report the following data: Library units Operating conditions Wire load models Cells (including cell exclusions, preferences, and other attributes) Compiler User GuideSpecifying Library ObjectsLibrary objects are the vendor-specific cells and their Design Compiler naming convention for library objects is[file:]library/cell[/pin]file:The file name of a technology library followed by a colon ( : ). Ifyou have multiple Libraries loaded in memory with the same name,you must specify the file name of a library in memory, followed by a slash ( / ).cellThe name of a library name of a cell s example, to set thedont_useattribute on the AND4 cell in themy_lib library, enterdc_shell>set_dont_use my_lib/AND4To set thedisable_timingattribute on the Z pin of the AND4 cellin the my_lib library, enterdc_shell>set_disable_timing find(pin, my_lib/AND4/Z) Compiler User GuideDirecting Library Cell UsageWhen Design Compiler maps a design to a technology library, itselects components (library cells) from that library.

9 You can influencethe choice of components (library cells) by Excluding cells from the target library Specifying cell preferencesExcluding Cells From the Target LibraryUse theset_dont_use command to exclude cells from the targetlibrary. Design Compiler does not use these excluded cells command affects only the copy of the library that is currentlyloaded into memory and has no effect on the version that exists ondisk. However, if you save the library, the exclusions are saved andthe cells are permanently example, to prevent Design Compiler from using the high-driveinverter INV_HD, enterdc_shell>set_dont_use MY_LIB/INV_HDPerforming set_dont_use on library cell MY_LIB/INV_HD .1 Use theremove_attributecommand to reinclude excluded cellsin the target >remove_attribute MY_LIB/INV_HD dont_usePerforming remove_attribute on library cell MY_LIB/INV_HD .1 Compiler User GuideSpecifying Cell PreferencesUse theset_prefercommand to indicate preferred cells.

10 You canissue this command with or without the-min the command without the-min option if you want DesignCompiler to prefer certain cells during the initial mapping of thedesign. Set the preferred attribute on particular cells to override the defaultcell identified by the library analysis step. This step occurs at thestart of compilation to identify the starting cell size for the initialmapping. Set the preferred attribute on cells if you know the preferredstarting size of those complex cells or cells with complex timingarcs (such as memories and banked components).You do not normally need to set the preferred attribute as part of yourregular compile methodology because the library analysis stepdetermines a good starting cell nonpreferred gates can be chosen to meet optimizationconstraints, the effect of preferred attributes might not be noticeableafter example, to set a preference for the low-drive inverter INV_LD,enterdc_shell>set_prefer MY_LIB/INV_LDPerforming set_prefer on library cell MY_LIB/INV_LD.