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1 DS92LV3241, SEPTEMBER2009 REVISEDAPRIL2013DS92LV3241/DS92LV324220- 85 MHz32-BitChannelLinkII serializer / DeserializerCheckforSamples:DS92LV3241, DS92LV32421 FEATURESAPPLICATIONS2 WideOperatingRangeEmbeddedClock IndustrialImaging(Machine-Vision)andSER/ DESC ontrol Upto32-bitParallelLVCMOSData Security& SurveillanceCamerasandInfrastructure 20to85 MHzParallelClock Medicalimaging Upto30bitsperPixel,VGAtoHDVideo SelectableSerialLVDSBusWidthTransportand Display DualLaneMode(20to50 MHz) QuadLaneMode(40to85 MHz)DESCRIPTION SimplifiedClockingArchitectureTheDS92LV3 241(SER)serializesa 32-bitdatabus NoSeparateSerialClockLineinto2 or4 (selectable)embeddedclockLVDS serialchannelsfora NoreferenceClockRequiredovercablessuchas CATx,orbackplanesFR-4 (DES)

2 On-ChipSignalConditioningforRobustSerial deserializesthe2 or4 LVDS serialdatachannels,Connectivityde-skewsc hannel-to-channeldelayvariationsandconve rtstheLVDS datastreambackintoa 32-bit TransmitPre-EmphasisLVCMOS paralleldatabus. DataRandomizationOn-chipdataRandomizatio n/ScramblingandDC DC-BalanceEncodingbalanceencodingandsele ctableserializerPre- ReceiveChannelDeskewemphasisensurea robust,low-EMItransmissionover , IntegratedLVDST erminationswithoutanexternalreferenceclo ckorspecialsync Built-inAT-SPEEDBISTforEnd-to-Endpattern s,providinganeasy plug-and-lock AC-CoupledInterconnectforIsolationandinc ludingsignalconditioningfunctions,theCha nnel-FaultProtectionLinkII SerDesdevicesreducetracecount,eliminate > 4 KVHBMESDP rotectionskewissues,simplifydesigneffort andlowercable/connectorcostforawidevarie tyofvideo, FullIndustrialTemperatureRange.

3 -40 toSPEEDBIST featurevalidateslinkintegrityandmay+85 ,standardwarranty,andusein 2009 2013, = L32 TxCLKINTx - SERIALIZERTxOUT0 NRT = 100:Rx - DESERIALIZERTxOUT0P32 RxCLKOUTQUADQUADRxIN0 NRxIN0 PDRRT = 100:TxOUT1 NRT = 100:TxOUT1 PRxIN1 NRxIN1 PDRRT = 100:RT = 100:DRRT = 100:RT = 100:DRRT = 100:(Dual Mode)(LVCMOS Input)DS92LV3242(20 MHz to 50 MHz)RxOUT(LVCMOS Output)(20 MHz to 50 MHz)LVCMOSDC Balance EncoderParallel-to-SerialTxIN0 ControlTxCLKINPre-EmpSerial-to-ParallelC ontrolDecoding, AlignmentLVCMOSCDR/PLLC able Deskew High-Speed Serial DataTxOUT0+TxOUT0 -TxOUT1+TxOUT1 -RxIN1 +RxIN0+RxIN0 -RxIN1 -PLLTx - SERIALIZERTxIN15 TxIN16 TxIN31 RxOUT0 RxCLKOUTRxOUT15 RxOUT16 RxOUT31100: differential pairsTxOUT2+TxOUT2 -TxOUT3+TxOUT3 -RxIN3 +RxIN2+RxIN2 -RxIN3 -Rx - DESERIALIZERMODEBISTENR_FBPDBVSELPRERENR _FBPDBLOCKBISTBISTDS92LV3241, DS92LV3242 SNLS314D SEPTEMBER2009 'DualMode2 SubmitDocumentationFeedbackCopyright 2009 2013,TexasInstrumentsIncorporatedProduct FolderLinks.

4 DS92LV3241DS92LV3242DS92LV32411211 MODE10R_FB9 BISTEN8 PDB7 TxCLKIN6 TxIN315 TxIN304 TxIN293 VDD2 TxIN25116151413 TxIN24 TxIN26 TxIN27 VSSTxIN2864 TxIN1963 TxIN1862 TxIN1761 TxIN1660 VDDPLL59 VSSPLL58 VSSPLL57 VDDPLL5655545352515049 TxIN20 TxIN21 TxIN22 TxIN23 TxIN15 TxIN14 IOVSSIOVDD171819202122232425262728 PREVSELTxOUT3-TxOUT3+TxOUT2-TxOUT2+VSSAV DDATxOUT1-TxOUT1+TxOUT0-TxOUT0+29303132 VDDVSSVSSVDD373839404142434445464748 TxIN2 TxIN3 TxIN4 TxIN5 TxIN6 TxIN7 TxIN8 VDDVSSTxIN9 TxIN12 TxIN1133343536 TxIN0 TxIN1 TxIN10 TxIN13 RSVDDS92LV3241 TxINMODE = H32 TxCLKINTx - SERIALIZERTxOUT0 NRT = 100:Rx - DESERIALIZERTxOUT0P32 RxCLKOUTQUADQUADRxIN0 NRxIN0 PDRRT = 100:TxOUT1 NRT = 100:TxOUT1 PRxIN1 NRxIN1 PDRRT = 100:TxOUT2 NRT = 100:TxOUT2 PRxIN2 NRxIN2 PDRRT = 100:TxOUT3 NRT = 100:TxOUT3 PRxIN3 NRxIN3 PDRRT = 100:(Quad Mode)(LVCMOS Input)DS92LV3242(40 MHz to 85 MHz)RxOUT(LVCMOS Output)(40 MHz to 85 MHz)DS92LV3241, SEPTEMBER2009 (PAGP ackage)Copyright 2009 2013,TexasInstrumentsIncorporatedSubmitD ocumentationFeedback3 ProductFolderLinks:DS92LV3241DS92LV3242D S92LV3241, DS92LV3242 SNLS314D SEPTEMBER2009 #PinNameI/O,TypeDescriptionLVCMOSPARALLE LINTERFACEPINS10 8,TxIN[31:29],I, 1,TxIN[28:24],64 57,TxIN[23:16],52 51,TxIN[15:14],48 [13:9],41 33 TxIN[8:0]11 TxCLKINI, , LVCMOSS erializerPowerDownBar(ACTIVELOW)PDB= L.

5 DeviceDisabled,Differentialserialoutputs areputintoTRI-STATE stand-bymode,PLLis shutdownPDB= H;DeviceEnabled15 MODEI, LVCMOSD ualorQuadmodeselect(ACTIVEH)MODE= L (default);DualMode,MODE= H;QuadMode19 PREI, LVCMOSPRE-emphasislevelselectpinPRE= (RPRE> 12k ); Imax= [( )x 20x 2],Rmin= 12k .PRE= H orfloating;pre-emphasisis , LVCMOSR ising/FallingBarClockEdgeSelectR_FB= H;RisingEdge,R_FB= L;FallingEdge20 VSELI, LVCMOSVOD(DifferentialOutputVoltage)Llev elSelectVSEL= L;LowSwing,VSEL= H;HighSwing13 BISTENI, LVCMOSBISTE nableBISTEN= L;BISTOFF,(default), H;BISTE nabled(ACTIVEHIGH)16 RSVDI, LVCMOSR eserved MUSTBETIEDLOWLVDSSERIALINTERFACEPINS22,2 4,TxOUT[3:0]+O,LVDSS erializerLVDSNon-InvertedOutputs(+)28,30 21,23,TxOUT[3:0]-O,LVDSS erializerLVDSI nvertedOutputs(-)27,29 POWER/ GROUNDPINS7,18,32,VDDVDDD igitalVoltagesupply, ,17,31,VSSGNDD igitalground4353,56 VDDPLLVDDA nalogVoltagesupply,PLLPOWER, ,55 VSSPLLGNDA nalogground, 2009 2013,TexasInstrumentsIncorporatedProduct FolderLinks.

6 DS92LV3241DS92LV3242DS92LV324212 VDD11 VSS10 RxOUT249 RxOUT258 RxOUT267 RxOUT276 RxOUT285 VDD4 VSS3 RxOUT292 VSSPLL116151413 VDDPLLLOCKRxCLKOUTRxOUT30 RxOUT3164 RxIN3-63 RxIN3+62 RxIN2-61 RxIN2+60 VSSA59 VDDA58 RxIN1-57 RxIN1+5655545352515049 VDDVSSVSSPLLVDDPLLRxIN0-RxIN0+RENPDB1718 19202122232425262728 RxOUT23 RxOUT22 RxOUT21 RxOUT20 RxOUT19 RxOUT18 RxOUT17 VDDVSSRxOUT16 RxOUT15 RxOUT1429303132 VSSVDDRxOUT13 RxOUT12373839404142434445464748 RxOUT9 RxOUT8 RxOUT7 RxOUT6 RxOUT5 VDDPLLVSSPLLRxOUT4 RxOUT3 RxOUT2 RxOUT033343536 RxOUT11 RxOUT10 RxOUT1R_FBRSVDDS92LV3241, SEPTEMBER2009 (PAGP ackage)Copyright 2009 2013,TexasInstrumentsIncorporatedSubmitD ocumentationFeedback5 ProductFolderLinks:DS92LV3241DS92LV3242D S92LV3241, DS92LV3242 SNLS314D SEPTEMBER2009 #PinNameI/O,TypeDescriptionLVCMOSPARALLE LINTERFACEPINS5 7,RxOUT[31:29],O, 14,RxOUT[28:24],19 25,RxOUT[23:17],28 32,RxOUT[16:12],33 39,RxOUT[11:5],42 46 RxOUT[4:0]4 RxCLKOUTO, ,LVCMOSLOCK indicatesthestatusofthereceiverPLLLOCK= L;deserializerCDR/PLLis notlocked,RxOUT[31:0]andRCLKareTRI-STATE DLOCK= H;deserializerCDR/PLLis lockedCONTROLANDCONFIGURATIONPINS48R_FBI , LVCMOSR ising/FallingBarClockEdgeSelectR_FB= H;RxOUTclockedonrisingedgeR_FB= L.

7 RxOUTclockedonfallingedge50 RENI, LVCMOSD eserializerEnable,DESO utputEnableControlInput(ACTIVEHIGH)REN= L;disabled,RxOUT[31:0]andRxCLKOUTTRI-STA TED,PLLstilloperationalREN= H;Enabled(ACTIVEHIGH)49 PDBI, LVCMOSP owerDownBar,ControlInputSignal(ACTIVELOW )PDB= L;disabled,RxOUT[31:0],RCLK,andLOCKareTR I-STATEDin stand-bymode,PLLis shutdownPDB= H;Enabled47 RSVDI, LVCMOSR eserved MUSTBETIEDLOWLVDSSERIALINTERFACEPINS51,5 3,RxIN[0:3]+I, LVDSD eserializerLVDSNon-InvertedInputs(+)57,5 952,54,RxIN[0:3]-I, LVDSD eserializerLVDSI nvertedInputs(-)58,60 POWER/ GROUNDPINS9,16,VDDVDDD igitalVoltagesupply, ,26,618,15,VSSGNDD igitalGround18,27,6255 VDDAVDDA nalogLVDSV oltagesupply,POWER, ,40,VDDPLLVDDA nalogVoltagesupplyPLLVCOPOWER, ,41,VSSPLLGNDA nalogground, 2009 2013,TexasInstrumentsIncorporatedProduct FolderLinks.

8 DS92LV3241DS92LV3242DS92LV3241, SEPTEMBER2009 REVISEDAPRIL2013 AbsoluteMaximumRatings(1)(2)SupplyVoltag e(VDD) +4 VLVCMOSI nputVoltage (VDD+ )LVCMOSO utputVoltage (VDD+ )LVDSD eserializerInputVoltage + + +125 CStorageTemperature 65 C to+150 CLeadTemperature(Soldering,4 seconds)+260 CMaximumPackagePowerDissipationCapacityP ackageDerating1/ JA C/Wabove+25 C C/W(3) C/WESDR ating(HBM)>4 kV(1) AbsoluteMaximumRatings indicatelimitsbeyondwhichdamagetothedevi cemayoccur, theRecommendedOperatingConditionsis functionalandthedeviceshouldnotbeoperate dbeyondsuchconditions.(2)If Military/Aerospacespecifieddevicesarereq uired,pleasecontacttheTexasInstrumentsSa lesOffice/Distributorsforavailabilityand specifications.

9 (3)4 LayerJEDECR ecommendedOperatingConditionsMinNomMaxUn itsSupplyVoltage(VDD) (IOVDD) (SERONLY) (TA) 40+25+85 CInputClockRateDualMode2050 MHzQuadMode4085 MHzTolerableSupplyNoise100mVP-PCopyright 2009 2013,TexasInstrumentsIncorporatedSubmitD ocumentationFeedback7 ProductFolderLinks:DS92LV3241DS92LV3242D S92LV3241, DS92LV3242 SNLS314D SEPTEMBER2009 (1)(2) :IOVDD= + :IOVDD= :IOVDD= :IOVDD= 18mA :VIN= ( ) 10+10 IOVDD= ( ) ARx:VIN= 10+10 VOHHighLevelOutputVoltageIOH= 2mA(Dual) 2mA(Quad)VOLLowLevelOutputVoltageIOH= 2mA(Dual) 2mA(Quad)IOSO utputShortCircuitCurrentVOUT= 0V(Dual) 22 40mAVOUT= 0V(Quad) 33 70mAIOZTRI-STATEO utputCurrentPDB= 0V, 10+10 AVOUT= 0 VorVDDSERIALIZERLVDSDCSPECIFICATIONSVODO utputDifferentialVoltageNopre-emphasis,V SEL= L350440525mVP-P(VSEL= H)(629)(850)(1000) VODO utputDifferentialVoltageUnbalanceVSEL= L,Nopre-emphasis150mVP-PVOSO ffsetVoltageVSEL= L, VOSO ffsetVoltageUnbalanceVSEL= L,Nopre-emphasis450mVIOSO utputShortCircuitCurrentTxOUT[3:0]= 0V,PDB= VDD, 2 5 VSEL= L,Nopre-emphasismATxOUT[3.]

10 0]= 0V,PDB= VDD, 6 10 VSEL= H,Nopre-emphasisIOZTRI-STATEO utputCurrentPDB= 0V, 15 1+15 ATxOUT[3:0]= 0 VORVDDPDB= VDD, 15 1+15 ATxOUT[3:0]= 0 VORVDDRTO utputTerminationInternaldifferentialoutp uttermination90100130 betweendifferentialpairsSERIALIZERSUPPLY CURRENT(DVDD,PVDDANDAVDDPINS)(3)IDDTQS erializer(Tx)TotalSupplyCurrentf = 85 MHz,CHECKERBOARD pattern150200 QuadModeMODE= H,VSEL= H,PRE= OFF(includesloadcurrent)f = 85 MHz,CHECKERBOARD pattern150200 MODE= H,VSEL= H,RPRE= 12k mAf = 85 MHz,RANDOM pattern140195 MODE= H,VSEL= H,PRE= OFFf = 85 MHz,RANDOM pattern140195 MODE= H,VSEL= H,RPRE= 12k (1)Typicalvaluesrepresentmostlikelyparam etricnormsatVDD= ,TA= +25 C,andattheRecommendedOperatingConditions atthetimeofproductcharacterizationandare notverified.