www.ti.com SPRS200N– JULY 2002– REVISED …

1 JULY2002 REVISEDOCTOBER2010 TMS320DM642 Video/ImagingFixed-PointDigitalSignalPro cessorCheckforSamples:TMS320DM6421 TMS320DM642 Video/ImagingFixed-PointDigitalSignalPro cessor123 1024M-ByteTotalAddressableExternal High-PerformanceDigitalMediaProcessorMem orySpace 2-, , EnhancedDirect-Memory-Access(EDMA) 500-, 600-,720-MHzClockRateController(64 IndependentChannels) Eight32-BitInstructions/Cycle 10/100Mb/sEthernetMAC(EMAC) 4000, 4800,5760 MIPS FullySoftware-CompatibleWithC64x MediaIndependentInterface(MII) ExtensionstoVelociTI 8 IndependentTransmit(TX)Channelsand1 AdvancedVery-Long-Instruction-Word(VLIW) Receive(RX)ChannelTMS320C64x DSPCore ManagementDataInput/Output(MDIO) EightHighlyIndependentFunctionalUnits Extensions: Providinga GluelessI/FtoCommonVideo SixALUs(32-/40-Bit),EachSupportsDecodera ndEncoderDevicesSingle32-Bit,Dual16-Bit, orQuad8-BitArithmeticperClockCycle SupportsMultipleResolutions/VideoStds TwoMultipliersSupportFour16x 16-Bit VCXOI nterpolatedControlPort(VIC)Multiplies(32 -BitResults)perClock SupportsAudio/VideoSynchronizationCycleo rEight8 x 8-BitMultiplies(16-Bit Host-PortInterface(HPI)[32-/16-Bit]Resul ts)perClockCycle 32-Bit/66-MHz, Load-StoreArchitectureWithNon-AlignedInt erconnect(PCI) 6432-BitGeneral-PurposeRegisters MultichannelAudioSerialPort(McASP) InstructionPackingReducesCodeSize EightSerialDataPins AllInstructionsConditional WideVarietyofI2S andSimilarBitStream InstructionSetFeaturesFormats Byte-Addressable(8-/16-/32-/64-BitData) IntegratedDigitalAudioI/FTransmitter 8-BitOverflowProtectionSupportsS/PDIF,IE C60958-1,AES-3,CP-430 Formats Bit-FieldExtract,Set,Clear Inter-IntegratedCircuit( I2C Bus )

2 Normalization,Saturation,Bit-Counting TwoMultichannelBufferedSerialPorts IncreasedOrthogonality Three32-BitGeneral-PurposeTimers L1/L2 MemoryArchitecture SixteenGeneral-PurposeI/O(GPIO)Pins 128K-Bit(16K-Byte)L1 PProgramCache(DirectMapped) FlexiblePLLC lockGenerator 128K-Bit(16K-Byte)L1 DDataCache(2-Way (JTAG)Boundary-Scan-CompatibleSet-Associ ative) 548-PinBallGridArray(BGA)Package 2M-Bit(256K-Byte)L2 UnifiedMapped(GDKandZDKS uffixes), (FlexibleRAM/CacheAllocation) 548-PinBallGridArray(BGA)Package Endianess:LittleEndian,BigEndian(GNZandZ NZS uffixes), 64-BitExternalMemoryInterface(EMIF) m/6-LevelCuMetalProcess(CMOS) GluelessInterfacetoAsynchronous , (-500)Memories(SRAMandEPROM)and , (A-500,A-600,-600,SynchronousMemories(SD RAM,SBSRAM,-720)ZBTSRAM,andFIFO)1 Pleasebeawarethatanimportantnoticeconcer ningavailability,standardwarranty,anduse in a Busis a 2002 2010, JULY2002 DSPs(includingtheTMS320DM642device)areth ehighest-performancefixed-pointDSPgenera tionintheTMS320C6000 (DM642)deviceis basedonthesecond-generationhigh-performa nce,advancedVelociTI very-long-instruction-word(VLIW)architec ture( ) developedbyTexasInstruments(TI), is a code-compatiblememberoftheC6000 (MIPS)ata clockrateof720 MHz, DSPcoreprocessorhas64general-purposeregi stersof32-bitwordlengthandeighthighlyind ependentfunctionalunits twomultipliersfora 32-bitresultandsixarithmeticlogicunits(A LUs)

3 Extensionsintheeightfunctionalunitsinclu denewinstructionstoacceleratetheperforma nceinvideoandimagingapplicationsandexten dtheparallelismoftheVelociTI (MACs)percyclefora totalof2880millionMACspersecond(MMACS),o reight8-bitMACspercyclefora ,on-chipmemory,andadditionalon-chipperip heralssimilartotheotherC6000 two-levelcache-basedarchitectureandhasa programcache(L1P)is a 128-KbitdirectmappedcacheandtheLevel1 datacache(L1D)isa memory/cache(L2) ,cache, :threeconfigurablevideoports;a10/100Mb/s EthernetMAC(EMAC);amanagementdatainput/o utput(MDIO)module;aVCXO interpolatedcontrolport(VIC);onemulticha nnelbufferedaudioserialport(McASP0);anin ter-integratedcircuit(I2C)Busmodule;twom ultichannelbufferedserialports(McBSPs);t hree32-bitgeneral-purposetimers;a user-configurable16-bitor32-bithost-port interface(HPI16/HPI32);a peripheralcomponentinterconnect(PCI);a 16-pingeneral-purposeinput/outputport(GP 0)withprogrammableinterrupt/eventgenerat ionmodes;anda64-bitgluelessexternalmemor yinterface(EMIFA), (VP0,VP1,andVP2).

4 Thesevideoportperipheralsprovidea ( ,CCIR601, , ,SMPTE125M,260M,274M,and296M). A andB witha 5120-bytecapture/displaybufferthatis ,seetheTMS320C64xDSPV ideoPort/VCXOI nterpolatedControl(VIC)PortReferenceGuid e(literaturenumberSPRU629).TheMcASP0port supportsonetransmitandonereceiveclockzon e, serialdatapinstransmittinga multitudeofvariationsonthePhilipsInter-I CSound(I2S) ,theMcASP0transmittermaybeprogrammedtoou tputmultipleS/PDIF,IEC60958,AES-3,CP-430 encodeddatachannelssimultaneously,witha ,suchasthebadclockdetectioncircuitforeac hhigh-frequencymasterclockwhichverifiest hatthemasterclockis withina 2002 2010,TexasInstrumentsIncorporatedSubmitD ocumentationFeedbackProductFolderLink(s) JULY2002 REVISEDOCTOBER2010 TheVCXO interpolatedcontrol(VIC) a ,seetheTMS320C64xDSPV ideoPort/VCXOI nterpolatedControl(VIC)PortReferenceGuid e(literaturenumberSPRU629).Theethernetme diaaccesscontroller(EMAC) ,or10 Mbits/second(Mbps)and100 Mbpsineitherhalf-orfull-duplex,withhardw areflowcontrolandqualityofservice(QOS) ,seetheTMS320C6000 DSPE thernetMediaAccessController(EMAC)/ ManagementDataInput/Output(MDIO)ModuleRe ferenceGuide(literaturenumberSPRU628).

5 Themanagementdatainput/output(MDIO) PHYcandidatehasbeenselectedbytheDSP, , ,seetheTMS320C6000 DSPE thernetMediaAccessController(EMAC)/ ManagementDataInput/Output(MDIO)ModuleRe ferenceGuide(literaturenumberSPRU628).Th eI2C0portontheTMS320DM642allowstheDSPtoe asilycontrolperipheraldevicesandcommunic atewitha ,thestandardmultichannelbufferedserialpo rt(McBSP)canbeusedtocommunicatewithseria lperipheralinterface(SPI) completesetofdevelopmenttoolswhichinclud es:a newCcompiler,anassemblyoptimizertosimpli fyprogrammingandscheduling,anda Windows a code-compatiblememberoftheC6000 DSPgenerationofdeviceshasa devices,seetheTMS320DM642 TechnicalOverview(literaturenumberSPRU61 5).Copyright 2002 2010,TexasInstrumentsIncorporatedTMS320D M642 Video/ImagingFixed-PointDigitalSignalPro cessor3 SubmitDocumentationFeedbackProductFolder Link(s):TMS320DM642 HPI32 ORHPI16 PCI-66 TestC64x DSP CoreData Path BB Register FileB31 B16B15 B0 Instruction FetchInstruction DispatchAdvanced Instruction PacketInstruction DecodeData Path AA Register FileA31 A16A15.

6 M1 ..M2 . CacheDirect-Mapped16K Bytes TotalControlRegistersControlLogicL1D Cache 2-Way Set-Associative16K Bytes TotalAdvancedIn-CircuitEmulationInterrup tControlTMS320DM642 EnhancedDMAC ontroller(EDMA)L2 CacheMemory256kBytesPLL(x1, x6, x12)Timer 2 EMIF AZBT SRAMT imer 1 Boot ConfigurationROM/FLASHI/O DevicesVideo Port 2(VP2)VCXOI nterpolatedControl Port(VIC)8/10-bit VP1 McBSP1(A)Video Port 1(VP1)ANDMcASP0 DataORORAND/OREMACMDIOORGP0I2C0162(B)8/1 0-bit VP0 McBSP0(A)Video Port 0(VP0)ANDMcASP0 ControlORORT imer 0 TMS320DM642 SPRS200N JULY2002 :FramingChips ,MVIP,SCSA,T1,E1;AC97 Devices;SPID evices; (VP0) (VP1) (32/16),EMAC, , 2002 2010,TexasInstrumentsIncorporatedSubmitD ocumentationFeedbackProductFolderLink(s) JULY2002 REVISEDOCTOBER20101 TMS320DM642 (EDMA) (DSPCore) (EMIF).. (McASP0) (I2C).. (HPI).. (PCI).. (McBSP).. (VIC).. (EMAC).. (MDIO).. (GPIO)..161(UnlessOtherwiseNoted).. (UnlessOtherwiseNoted).

7 2002 2010,TexasInstrumentsIncorporatedContent s5 SubmitDocumentationFeedbackProductFolder Link(s):TMS320DM642 TMS320DM642 SPRS200N JULY2002 ,includingthecapacityofon-chipRAM,theper ipherals,theCPUfrequency, (64-bitbuswidth)1(clocksource= AECLKIN)EDMA(64independentchannels)1 McASP0(usesPeripheralClock[AUXCLK])1I2C0 (usesPeripheralClock)1 HPI(32-or16-bituserselectable)1 (HPI16orHPI32)PeripheralsPCI(32-bit),66- MHz/33-MHz1[DeviceIDRegistervalue0x9065] Notallperipheralspinsareavailableatthesa metimeMcBSPs2(Formoredetail,seethe(inter nalclocksource= CPU/4clockfrequency)DeviceConfigurationC onfigurableVideoPorts(VP0,VP1,VP2)3secti on).10/100 EthernetMAC(EMAC)1 ManagementDataInput/Output(MDIO)1 VCXOI nterpolatedControlPort(VIC)132-BitTimers 3(internalclocksource= CPU/8clockfrequency)General-PurposeInput /OutputPort(GP0)16 Size(Bytes)288K16K-Byte(16KB)L1 Program(L1P)CacheOn-ChipMemoryOrganizati on16 KBL1 Data(L1D)Cache256 KBUnifiedMappedRAM/Cache(L2)CPUID+ CPURevIDControlStatusRegister(CSR.)

8 [31:16])0x0C01 JTAGBSDL_IDJTAGID register(addresslocation:0x01B3F008)0x00 07902 FFrequencyMHz500, 600,7202 ns(DM642-500)and(DM642A-500)[500 MHzCPU,100 MHzEMIF(1), 33 MHzPCIport] (DM642-600)and(DM642A-600)CycleTimens[60 0 MHzCPU,133 MHzEMIF(1), 66 MHzPCIport] (DM642-720)[720 MHzCPU,133 MHzEMIF(1), 66 MHzPCIport] ( 500)Core(V) (A-500,A-600,-600,-720)VoltageI/O(V) (x1),x6,x1223x 23mm548-PinBGA(GDKandZDK)BGAP ackage(2)27x 27mm548-PinBGA(GNZandZNZ)ProcessTechnolo gy mProductPreview(PP),AdvanceInformation(A I),ProductStatus(3)PDorProductionData(PD )(1)OnthisDM64x device, ,seetheEMIF devicespeedportionofthisdatasheet.(2)For theexactmarkingsofpinA1,seetheTMS320DM64 2 DigitalSignalProcessorSiliconErrata(Lite ratureNumber:SPRZ196).(3)PRODUCTIONDATA informationis 2002 2010,TexasInstrumentsIncorporatedSubmitD ocumentationFeedbackProductFolderLink(s) JULY2002 (DSPCore)DescriptionTheCPUfetchesVelociT I advancedvery-longinstructionwords(VLIWs) (256bitswide) VLIW architecturefeaturescontrolsbywhichallei ghtunitsdonothavetobesuppliedwithinstruc tionsif thenextinstructionbelongstothesameexecut epacketasthepreviousinstruction,orwhethe rit shouldbeexecutedinthefollowingclockasa ;however, , extensionsaddenhancementstotheTMS320C62x DSPV elociTI : Registerfileenhancements Datapathextensions Quad8-bitanddual16-bitextensionswithdata flowenhancements Additionalfunctionalunithardware Increasedorthogonalityoftheinstructionse t.

9 S1,.M1, ; ,.M2,.S2, VelociTI VLIW architecture,theC64x ,alongwithtworegisterfiles,composesidesA andB oftheCPU[seethefunctionalblockandCPU(DSP core)diagram,andFigure2-1]. ,eachsidefeaturesa "datacrosspath" a singledatabusconnectedtoalltheregisterso ntheotherside, ,adelayclockis introducedwheneveraninstructionattemptst oreada registerviaa datacrosspathif thatregisterwasupdatedin DSPfixed-pointinstructions,theC64x a ,whereallinstructionsoperateonregisters( asopposedtodatainmemory).Twosetsofdata-a ddressingunits(. ) (8bits),half-words(16bits),andwords(32bi ts)witha , (64bits)witha , , ,however,aresingledouttosupportspecifica ddressingmodesortoholdtheconditionforcon ditionalinstructions(iftheconditionis notautomatically"true").Copyright 2002 2010,TexasInstrumentsIncorporatedDeviceO verview7 SubmitDocumentationFeedbackProductFolder Link(s):TMS320DM642 TMS320DM642 SPRS200N JULY2002 16-bitmultipliesorfour8 32-bitmultiplyoperations,dual16 16-bitmultiplieswithadd/subtractoperatio ns,andquad8 , ,rotate,Galoisfieldmultiplies, generalsetofarithmetic,logical, ,dual16-bit, 256-bit-wideinstructionfetchpacketisfetc hedfroma "linked"togetherby"1"bitsin theleastsignificantbit(LSB) "chained"togetherforsimultaneousexecutio n(uptoeightintotal) "0"intheLSBofaninstructionbreaksthechain ,effectivelyplacingtheinstructionsthatfo llowit /TMS320C67x DSPdevices,if anexecutepacketcrossesthefetch-packetbou ndary(256bitswide)

10 ,theassemblerplacesit inthenextfetchpacket, DSPdevice,theexecuteboundaryrestrictions havebeenremoved,thereby,eliminatingallof theNOPsaddedtopadthefetchpacket,andthus, ,theinstructionssimultaneouslydriveallac tivefunctionalunitsfora ,theycanbesubsequentlymovedtomemoryasbyt es,half-words, ,half-word-,word-, ,seethefollowingdocuments: TMS320C6000 CPUandInstructionSetReferenceGuide(liter aturenumberSPRU189) TMS320C64xTechnicalOverview(literaturenu mberSPRU395)8 DeviceOverviewCopyright 2002 2010,TexasInstrumentsIncorporatedSubmitD ocumentationFeedbackProductFolderLink(s) dst88src2DA1 (Address)ST1b (Store Data)ST2a (Store Data)RegisterFile A(A0 A31)8888dstData Path ADA2 (Address)RegisterFile B(B0 B31)LD2a (Load Data)Data Path BControl RegisterFileST2b (Store Data)LD1b (Load Data)882X1 XST1a (Store Data)(A)LD1a (Load Data)LD2b (Load Data)32 MSBs32 LSBs32 MSBs32 LSBs32 MSBs32 LSBs32 MSBs32 LSBssrc2src1dstlong dstlong srclong srclong dstdstsrc1src2src1src2src2src1dstsrc2src 1dstsrc2long dstsrc2src1dstlong dstlong dstlong srclong srclong dstdstdstsrc2src1dst(A)(A)(A) JULY2002 ,thelongdstis 32 MSBsandthedstis CPU(DSPCore)DataPathsCopyright 2002 2010,TexasInstrumentsIncorporatedDeviceO verview9 SubmitDocumentationFeedbackProductFolder Link(s).