Xilinx Answer 60305 MIG UltraScale DDR4/DDR3 - …

1 Copyright 2012 Xilinx Xilinx Answer 60305 UltraScale MIG DDR4/DDR3 - hardware Debug Guide 1 Xilinx Answer 60305 MIG UltraScale DDR4/DDR3 - hardware Debug Guide Important Note: This downloadable PDF of an Answer Record is provided to enhance its usability and readability. It is important to note that Answer Records are Web-based content that are frequently updated as new information becomes available. You are reminded to visit the Xilinx Technical Support Website and review ( Xilinx Answer 60305 ) for the latest version of this Answer Record.

2 Introduction Calibration failures and data errors can occur for many reasons and the debug of these errors can be time consuming. This Answer record is intended to provide a clear step-by-step debug process to quickly identify the root cause of the failure and move to resolution. MIG Usage To focus the debug of calibration or data errors, use the provided MIG Example Design on the targeted board with the Debug Feature enabled through the MIG UltraScale GUI. Note, use of the MIG Example Design and enabling of the Debug Feature is not required to capture calibration and window results using XSDB, but it is useful to focus the debug on a known working solution.

3 However, the Debug Signals and Example Design are required to analyze the provided ILA and VIO debug signals within the Vivado Lab Tools. The latest MIG release should be used to generate the Example Design. Debug Tools Many tools are available to debug memory interface design issues. This section indicates which resources are useful for debugging a given situation. XSDB Debug MIG includes XSDB debug support. The MIG IP stores useful core configuration, calibration, and data window information within internal BRAM. The MIG Debug XSDB interface can be used at any point to read out this information and get valuable statistics and feedback from the MIG IP. The information can be viewed through a MIG Debug GUI or through available MIG Debug Tcl commands.

4 MIG Debug GUI Usage Upon configuring the device the MIG debug core and contents will be visible in hardware Manager. Copyright 2012 Xilinx Xilinx Answer 60305 UltraScale MIG DDR4/DDR3 - hardware Debug Guide 2 Figure 1: MIG Debug Core Unit, Properties, and Configuration Windows Copyright 2012 Xilinx Xilinx Answer 60305 UltraScale MIG DDR4/DDR3 - hardware Debug Guide 3 Figure 2: Example Display of MIG Debug Core Figure 3: Example of Refresh Device Copyright 2012 Xilinx Xilinx Answer 60305 UltraScale MIG DDR4/DDR3 - hardware Debug Guide 4 MIG Debug Tcl Usage The following Tcl commands are available from the Vivado Tcl Console when connected to the hardware .

5 This will output all XSDB MIG content that is displayed in the GUIs. get_hw_migs Displays what MIG cores exist in the design refresh_hw_device Refreshes the whole device including all cores refresh_hw_mig [lindex [get_hw_migs] 0] Refreshes only the MIG core denoted by index (index begins with 0). report_propery [lindex [get_hw_migs] 0] Reports all of the parameters available for the MIG core. Where 0 is the index of the MIG core to be reported (index begins with 0). report_debug_core Reports all debug core peripherals connected to the Debug Hub dbg_hub Associates the debug core Index with the Instance Name Useful when multiple instances of MIG IP are instantiated within the design to associate the debug core index with the each IP instantiation.

6 Report_debug_core example: Peripherals Connected to Debug Hub 'dbg_hub' (2 Peripherals): +-------+------------------------------+ ----------------------------------+ | Index | Type | Instance Name | +-------+------------------------------+ ----------------------------------+ | 0 | vio_v3_0 | gtwizard_ultrascale_0_vio_0_inst | +-------+------------------------------+ ----------------------------------+ | 1 | labtools_xsdb_slave_lib_v2_1 | your_instance_name | +-------+------------------------------+ ----------------------------------+ | 2 | labtools_xsdb_slave_lib_v2_1 | your_instance_name | +-------+------------------------------+ ----------------------------------+ | 3

7 | labtools_xsdb_slave_lib_v2_1 | your_instance_name | +-------+------------------------------+ ----------------------------------+ | 4 | labtools_xsdb_slave_lib_v2_1 | your_instance_name | +-------+------------------------------+ ----------------------------------+ Example Design Generation of a DDR4 or DDR3 design through the MIG tool allows an example design to be generated using the Vivado Generate IP Example Design feature. The example design includes a synthesizable testbench with a traffic generator that is fully verified in simulation and hardware . This example design can be used to observe the behavior of the MIG design and can also aid in identifying board-related problems.

8 For complete details on the example design, see the Example Design section in the LogiCore IP UltraScale -Based FPGAs Memory Interface Solutions Product Guide (PG150). This debug guide Answer record further describes using the example design to perform hardware validation. Debug Signals The MIG UltraScale designs include an XSDB debug interface that can be used to very quickly identify calibration status and read and write window margin. This debug interface is always included in the generated MIG UltraScale designs. Additional debug signals for use in Vivado Lab Tools can be enabled using the Debug Signals option on the FPGA Options MIG GUI screen. Enabling this feature allows example design signals to be monitored using the Vivado Lab Tools.

9 Selecting this option brings the debug signals to the top-level and creates a sample ILA core that debug signals can be port mapped into. Additionally, a VIO core can be added as needed. For details on enabling this debug feature, see the Customizing and Generating the Core section in the LogiCore IP UltraScale -Based FPGAs Memory Interface Copyright 2012 Xilinx Xilinx Answer 60305 UltraScale MIG DDR4/DDR3 - hardware Debug Guide 5 Solutions Product Guide (PG150). The debug port is disabled for functional simulation and can only be enabled if the signals are actively driven by the user design.

10 Reference Boards The KCU105 evaluation kit is a Xilinx development board that includes FPGA interfaces to a 64-bit (4 x16 components) DDR4 interface. This board can be used to test user designs and analyze board layout. Vivado Lab Tools The Vivado Lab Tools insert logic analyzer, bus analyzer, and VIO software cores directly into the design. The Vivado Lab Tools allows the user to set trigger conditions to capture application and MIG signals in hardware . Captured signals can then be analyzed. General Checks This section details the list of general checks, primarily board level, which need to be verified before moving forward with the debug process. Strict adherence to the proper board design is critical in working with high speed memory interfaces.