Xilinx UG070 Virtex-4 FPGA User Guide, User Guide

1 RVirtex-4 FPGA user GuideUG070 ( ) December 1, 2008 Virtex-4 FPGA user ( ) December 1, 2008 Xilinx is disclosing this user Guide , manual, release note, and/or specification (the "Documentation") to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the Documentation in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior written consent of Xilinx . Xilinx expressly disclaims any liability arising out of your use of the Documentation. Xilinx reserves the right, at its sole discretion, to change the Documentation without notice at any time.

2 Xilinx assumes no obligation to correct any errors contained in the Documentation, or to advise you of any corrections or updates. Xilinx expressly disclaims any liability in connection with technical support or assistance that may be provided to you in connection with the DOCUMENTATION IS DISCLOSED TO YOU AS-IS WITH NO WARRANTY OF ANY KIND. Xilinx MAKES NO OTHER WARRANTIES, WHETHER EXPRESS, IMPLIED, OR STATUTORY, REGARDING THE DOCUMENTATION, INCLUDING ANY WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NONINFRINGEMENT OF THIRD-PARTY RIGHTS. IN NO EVENT WILL Xilinx BE LIABLE FOR ANY CONSEQUENTIAL, INDIRECT, EXEMPLARY, SPECIAL, OR INCIDENTAL DAMAGES, INCLUDING ANY LOSS OF DATA OR LOST PROFITS, ARISING FROM YOUR USE OF THE DOCUMENTATION.

3 2004 2008 Xilinx , Inc. Xilinx , the Xilinx logo, virtex , Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. The PowerPC name and logo are registered trademarks of IBM Corp. and used under license. All other trademarks are the property of their respective HistoryThe following table shows the revision history for this document. RDateVersionRevision08/02 Xilinx release. Printed Handbook Chapter 1, Clock Resources :Removed Table 1-6: "BUFGMUX_VIRTEX4 Attributes". Updated Ta b l e 1 -1, Ta b l e 1 - 2, Ta b l e 1 - 5, the new Ta b l e 1 - 6. Revised Figure 1-2, Figure 1-5, Figure 1-6, Figure 1-7, Figure 1-9, Figure 1-10, Figure 1-13, Figure 1-14, and Figure 1-16.

4 Associated text around these tables and figures were revised. In Chapter 2, Digital Clock Managers (DCMs) , changes to FACTORY_JF Attribute and in Ta b l e 2 - Chapter 9, System Monitor :Changed in Figure 9-4, Figure 9-5, Figure 9-7, Figure 9-8, Figure 9-9, Figure 9-10, Figure 9-21, Figure 9-25, Figure 9-26, and Figure 9-27. Changes to the equation in the Temperature Sensor section. The following tables had changes: Table 9-3, Table 9-5, Table 9-6, Table 9-9, Table 9-11, Table 9-12, Table 9-14, and Table 9-15. Changes to the entire System Monitor Calibration, System Monitor VHDL and Verilog Design Example Chapter 1, Clock Resources , revised Global Clock Buffers , Clock Regions , and Clock Capable I/O Chapter 4, Block RAM, revised Reset, page 151 description and Ta b l e 4 - 1 Chapter 6, SelectIO Resources, removed the device configuration section.

5 The Virtex-4 Configuration Guide describes this information in detail. Edited SSTL (Stub-Series Terminated Logic), page 281. Replaced LVDS_25_DCI with LVDCI_25 in Compatible example:, page 302. Added rule 7 to DCI in Virtex-4 FPGA Hardware, page 241. Added Simultaneous Switching Output Limits, page 306. Removed Chapter 9: System ( ) December 1, FPGA user Guide04/11 1: Revised Ta b l e 1 -1 , p a g e 2 6, Figure 1-14, and BUFR Attributes and Modes section including Figure 1-21, page 43. Chapter 2: Revised FACTORY_JF value in Ta b l e 2 - 6 , p a g e 6 5. Added Phase-Shift Overflow section. Clarified global clock discussion in Global Clock Buffers , Clock Regions , and Clock Capable I/O .Chapter 4: Added Built-in Block RAM Error Correction Code section.

6 Revised Figure 4-6 and Figure 4-8, page 123. Chapter 5: Revised Ta b l e 5 - 1 and Table 5-2, page 6: Revised Table 6-29, page 290. Chapter 7: Revised REFCLK - Reference Clock and added Table 7-10, page 8: Added ISERDES Latencies, page 379 and OSERDES Latencies, page 394. Revised Guidelines for Using the Bitslip Submodule 2: Revised FACTORY_JF value in Ta b l e 2 - 6 , p a g e 6 5. The LOCKED signal description is updated in Figure 2-20 and Figure 6: Revised the Simultaneous Switching Output Limits 8: Added more information to Clock Enable Inputs CE1 and CE2, page 1: Updated description under Ta b l e 1 -1. Updated Figure 1-21, page 4: Changed Table 4-8, page 144 and added a note. Updated the discussions in NO_CHANGE Mode and Cascadable Block RAM sections.

7 Removed synchronous FIFO application 5: Revised slice label in Figure 5-30, page 6: Added to the Xilinx DCI section. Added IBUF to the PULLUP/PULLDOWN/KEEPER for IBUF, OBUFT, and IOBUF discussion. Added VCCO numbers in the + column in Table 6-5, page 258. Corrected Figure 6-70, page 292. Added notes 4 and 5 to Table 6-38, page 299. Updated I/O Design Guidelines Summary, page 306. Added HSLVDCI (High-Speed Low Voltage Digitally Controlled Impedance), page 259 section. Added to Table 6-40, page 308, and added link to SSO calculator to text above table. Added HSLVDCI to Table 6-42, page 310. Revised Virtex-4 (SX Family) FF668 in Ta b l e 6 - 4 3. Chapter 8: Revised Clock Enable Inputs CE1 and CE2 . Chapter 9, Temperature Sensing Diode : Added the Virtex-4 temperature-sensing 7, SelectIO Logic Resources : Modified text in section REFCLK - Reference Clock and deleted former Table FPGA user ( ) December 1, 200801/04 Chapter 1, Clock Resources : I/O Clock Buffer - BUFIO : Added in the same region to BUFIO ability to drive BUFRs.

8 BUFG VHDL and Verilog Templates : Corrected typo in VHDL template. Regional Clocks and I/O Clocks : Added reference to the PACE tool for identifying clock regions. Chapter 2, Digital Clock Managers (DCMs) : Status Flags : Corrected descriptions for Clock Events 2, 3, and 4. Input Clock Requirements : Clarified when DCM output clocks are deskewed. Reset Input RST : Updated RST hold time to 200 ms after clock stabilization. Frequency Synthesizer Characteristics : Added reference and link to a macro for monitoring LOCKED. Chapter 4, Block RAM : Data Flow : Added paragraph clarifying ADDR setup/hold requirements. Ta b l e 4 - 11: Corrected typo to ALMOST FULL. RAMB16 Port Mapping Design Rules : Corrected logic level tie for unused ADDR[A|B] pins to High.

9 Synchronous Clocking : Clarified synchronous write/read timing. Deleted SIM_COLLISION_CHECK statements from all templates. Chapter 6, SelectIO Resources : Figure 6-53: Corrected internal termination resistor designation. Ta b l e 6 - 1: Updated LVTTL DC voltage specifications. Ta b l e 6 - 3 1 and following: Globally corrected OBUFGDS to OBUFTDS. Differential Termination Attribute : Corrected paragraph describing use of DIFF_TERM attribute. Xilinx DCI : Added reference to section Driver with Termination to VCCO / 2 (Split Termination). Figure 6-64: Corrected I/O standard name to DIFF_SSTL2_II. Ta b l e 6 - 3 8: Corrected I/O standard name to DIFF_HSTL_II_18_DCI. Chapter 7, SelectIO Logic Resources : IDELAYCTRL Locations : Reworded description of IDELAYCTRL locations in clock regions.

10 Ta b l e 7 - 6: Added when in Variable mode to function descriptions of C, INC, and CE ports. Ta b l e 7 - 9: Added Note (1) to TIDELAYRESOLUTION. Added requirement to wait 8 clock cycles after increment or decrement before sampling IDELAY. Figure 7-12: Modified to show 8 clock cycle wait time. Modified timing description to match new Figure 7-12. IDELAY VHDL and Verilog Instantiation Template : Changed port map for C, CE, INC, and RST from open to zero (both Verilog and VHDL). Deleted synthesis translate_off/synthesis translate_on statements from all IDELAY instantiation ( ) December 1, FPGA user Guide01/04/07(cont d) (cont d) Chapter 8, Advanced SelectIO Logic Resources : Ta b l e 8 - 1: REV: Added instruction to connect to GND.