Intel Stratix 10
Intel Stratix 1 0Intel Stratix 10 Mx (DraM SySteM-In-Package) ProDuct tableNotes:1. LE counts valid in comparing across Altera devices, and are conservative vs. competing Fixed point performance assumes the use of Floating-point performance is IEEE-754 compliant Quad-core ARM Cortex-A53 hard processor system not available in Stratix 10 MX A subset of pins for each package are used for high-voltage V and V All data is preliminary and subject to change without prior LINEMX 1650MX 1650MX 1650MX 2100MX 2100MX 2100MX 2100ResourcesLogic elements (LEs)11,679,0001,679,0001,679,0002,073,0 002,073,0002,073,0002,073,000Adaptive logic modules (ALMs)569,200569,200569,200702,720702,72 0702,720702,720ALM registers2,276,8002,276,8002,276,8002,81 0,8802,810,8802,810,8802,810,880Hyper-Re gisters from Intel HyperflexTM FPGA architectureMillions of Hyper-Registers distributed throughout the monolithic FPGA fabricProgrammable clock trees synthesizableHundreds of synthesizable clock treesHBM2 high-bandwidth DRAM memory (GBytes)816888168eSRAM memory blocks2222222eSRAM memory size (Mb) memory blocks6,1626,1626,1626,8476,8476,8476,84 7M20K memory size (Mb)120120120134134134134MLAB memory size (Mb)99911111111Variable-precision digital signal processing (DS)
Intel® Stratix® 10 Intel ® StratIx® 10 Mx (DraM SySteM-In-Package) ProDuct table Notes: 1. LE counts valid in comparing across Intel FPGA devices, and are conservative vs. competing FPGAs. 2. Fixed-point performance assumes the use of pre-adder.
Download Intel Stratix 10
Information
Domain:
Source:
Link to this page:
Please notify us if you found a problem with this document: