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Lecture 13 - MIT

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In practice many gates do not change state every clock cycle which lowers the power dissipation. 6.012 Spring 2007 Lecture 13 14 CMOS Static Logic Gates V OUT V DD V DD A M 1 B M 3 M 4 M 2 M 1 M 2 M 3 M 4 A A B A B (a) (b) B + _ V OUT + _ 6.012 Spring 2007 Lecture 13 15 CMOS NAND Gate I-V Characteristics of n-channel devices V DD V DS1 M 3 4 M ...

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