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SEMICONDUCTOR MEMORIES

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Digital Integrated Circuits Prentice Hall 1995MemorySEMICONDUCTORMEMORIESDigital Integrated Circuits Prentice Hall 1995MemoryChapter Overview Memory Classification Memory Architectures The Memory Core Periphery ReliabilityDigital Integrated Circuits Prentice Hall 1995MemorySemiconductor MemoryClassificationRWMNVRWMROMEPROME2PR OMFLASHRandomAccessNon-RandomAccessSRAM DRAMMask-ProgrammedProgrammable (PROM)FIFOShift RegisterCAMLIFODigital Integrated Circuits Prentice Hall 1995MemoryMemory Architecture: DecodersWord 0Word 1Word 2Word N-1Word N-2Input-OutputS0S1S2SN-2SN_1(M bits)StorageCellM bitsN WordsWord 0Word 1Word 2Word N-1Word N-2Input-Output(M bits)StorageCellM bitsDecoderA0A1AK-1S0N words => N select signalsToo many select signalsDeco

Metal1 on top of diffusion Basic cell 10 λ x 7 λ 2 λ WL[0] WL[1] WL[2] WL[3] GND (diffusion) Metal1 Polysilicon Only 1 layer (contact mask) is used to program memory array Programming of the memory can be delayed to one of last process steps

  Diffusion

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