Semiconductor Packing Methodology (Rev. C)
Application ReportSZZA021C September 20051Semiconductor Packing MethodologyCles Troxtell, Bobby O Donley, Ray Purdom, and Edgar ZunigaStandard Linear & LogicABSTRACTThe Texas Instruments Semiconductor Group uses three Packing methodologies to preparesemiconductor devices for shipment to end users. The methods employed are linked to thedevice level for shipping configuration keys. End users of the devices often need to perusemany TI and industry publications to understand the shipping configurations. This applicationreport documents TI s three main shipping methods and typical dimensions for end users . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Background3.
SZZA021C Semiconductor Packing Methodology 3 Introduction This application report describes in detail the methods used by the TI Standard Linear & Logic
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