Sequential 4-bit Adder Design Report - ianhung

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UNIVERSITY OF WATERLOO. Faculty of Engineering E&CE 438: Digital Integrated Circuits Sequential 4-bit Adder Design Report Prepared by: Ian Hung (iXXXXXX), 99XXXXXX. Annette Lo (aXXXXXX), 99XXXXXX. Pamela Torres (pXXXXXX), 99XXXXXX. August 8, 2003. Table of Contents List of Figures ........................................ ........................................ .................................... iii List of Tables ........................................ ........................................ ..................................... iv 1. Project Requirements ........................................ ........................................ .................... 1. Functionality of Binary Adder .

2 Figure 1: Sequential 4-bit Adder Layout 2.1 Adder Architecture Selection The three main adder designs considered include complementary static CMOS, mirror,

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