Sequential 4-bit Adder Design Report - ianhung

UNIVERSITY OF WATERLOO. Faculty of Engineering E&CE 438: Digital Integrated Circuits Sequential 4-bit Adder Design Report Prepared by: Ian Hung (iXXXXXX), 99 XXXXXX. Annette Lo (aXXXXXX), 99 XXXXXX. Pamela Torres (pXXXXXX), 99 XXXXXX. August 8, 2003. Table of Contents List of Figures .. iii List of Tables .. iv 1. Project Requirements .. 1. Functionality of Binary Adder .. 1. Design 2. Adder Architecture 2. Flip-flop Architecture Selection .. 6. Optimization Techniques .. 6. Sizing .. 6. Pre-layout Simulation 8. Layout of Sequential Four-Bit Adder .. 9. Post-layout Simulation Results .. 10. 11. 12. Appendix .. A-1. ii List of Figures Figure 1: Sequential 4-bit Adder Layout.

2 Figure 1: Sequential 4-bit Adder Layout 2.1 Adder Architecture Selection The three main adder designs considered include complementary static CMOS, mirror,

Loading..

Tags:

  Design, Report, Sequential, Dread, Sequential 4 bit adder design report ianhung, Ianhung, Sequential 4, Bit adder

Information