Software Developer Guide - Xilinx
zynq UltraScale+ MPSoCSoftware Developer GuideUG1137 ( ) July 1, 2020Revision HistoryThe following table shows the revision history for this Summary07/01/2020 Version 10: Platform Management Unit FirmwareUpdated PMU Firmware Build Flags to add a new 12: ResetUpdated RPU Subsystem Restart for RPU only restartsupport E: XilSecure Library Additional H: XilFPGA Library Additional Version Embedded FlowUpdated SDK flows to Vitis Embedded Flow throughout Version 4: Software StackUpdated Multimedia Stack 7: System Boot and ConfigurationUpdated Miscellaneous FunctionsChapter 10: Platform Management Unit FirmwareAdded CSU/PMU Register Access and updated PMUFirmware Build FlagsChapter 11: Power Management FrameworkUpdated Sub-system Power ManagementAdded appendix01/18/2019 Version 2: Programming View of zynq UltraScale+ MPSoCDevicesUpdated Boot Modes and System-Level Protections sectionsChapter 3: Development ToolsAdded Device Tree GeneratorChapter 4: Software StackRemoved XilRSA referencesChapter 8: Security FeaturesUpdated Configuring XMPU RegistersChapter 9: Platform ManagementUpdated Power Management FrameworkChapter 10: Platform Management Unit FirmwareUpdated PMU Firmware Build Flags, FPD WDT, and PMUFirmware Memory Layout and FootprintChapter 12: ResetUpdated Warm Restart with a note about on-chip memory(OCM)Chapter 16: Boot Image Crea
Chapter 11: Power Management Framework Updated Zynq UltraScale+ MPSoC Power Management Software Architecture, Using the API for Power Management , Sub-system Power Management, and XilPM Implementation Details sections Chapter 16: Boot Image Creation Updated BIF File Parameters, Boot Image Format and Boot Header Table. 05/03/2017 Version …
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