STA - Static Timing Analysis - BGU

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STA - Static Timing AnalysisSTALecturer: Gil RahavSemester B , EE Dept. Semiconductors IsraelStatic Verification FlowFunctionalFunctionalSimulationSimula tionScanScanSynthesisSynthesisPlacePlace TestbenchTestbenchClockClockTreeTreeRout eRouteRTL DomainGate-level DomainStatic Timing AnalysisStatic Timing AnalysisEquivalence CheckingEquivalence CheckingEquivalence Equivalence CheckingCheckingSignOffWhat is Static Verification? Static verification: Verifies Timing andfunctionality STA andequivalence checking Is exhaustive Uses formal, mathematical techniques insteadof vectors Does notuse dynamic logic simulationStatic Timing Analysis FlowEvery Corner and ModeErrors/Warnings?Fix dataNext step in designflowAnalyze ReportsRead required filesValidate inputsnoyesReady to perform STAon a gate-levelsynchronous designusing SDFPrimeTimeRequired Input FilesSynthesis technology librarySynthesis technology libraryDesignconstraints in TclDesignconstraints in TclSDFSDFDelay CalculatorGate-level netlistGate-level netlistTimingmodellibraryTimingmodellibr aryErrors/Warnings?

Static Verification Flow Functional Simulation Scan Synthesis Place Testbench Clock Tree Route RTL Domain Gate-level Domain Static Timing Analysis …

  Analysis, Static, Timing, Static timing analysis