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Verilator - Veripool

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Verilator Release Wilson Snyder 2022-01-19. GETTING STARTED. 1 Overview 1. 2 Examples 2. Example C++ Execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2. Example SystemC Execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3. Examples in the Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4. 3 Installation 6. Package Manager Quick Install . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6. Git Quick Install . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6. Detailed Build Instructions.

Verilog-XL/NC-Verilog, or Synopsys VCS. Verilator reads the specified SystemVerilog code, lints it, optionally adds coverage and waveform tracing support, and compiles the design into a source level multithreaded C++ or SystemC “model”. The resulting model’s C++ or SystemC code is output as .cpp and .h files.

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