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CADENCE TUTORIAL

1 CADENCE TUTORIALSan Diego State University,Department of Electrical and Computer EngineeringAmith Dharwadkar and Ashkan Ashrafi2 Contents1) 32)Connecting to the Volta )Creating a work )RTL )NETLIST )Layout TUTORIAL is aimed at introducing a user to the CADENCE tool. It gives step by step approachto performing a RTL simulation, gate level synthesis/simulation and finally layout design usingSOCENCOUNTER sautoplaceandroute with TSMC m standard cell library. Thetutorialhowever does not discuss installation and environment setup for CADENCE . The entiretutorial is organized into five chapters beginning with connecting toVoltaserver on whichCADENCE resides.

There are two approaches to doing this. We can either use the Verilog-XL compiler or use NCVERILOG/NCSIM. Chapter 2 talked about using Verilog-XL for carrying out RTL simulation. The same procedure could be used for simulating the netlist file. However, we will have to include TSMC 0.13um standard cell library files tcb013ghp.vand tpd013n2.v

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