Transcription of CADENCE TUTORIAL
1 1 CADENCE TUTORIALSan Diego State University,Department of Electrical and Computer EngineeringAmith Dharwadkar and Ashkan Ashrafi2 Contents1) 32)Connecting to the Volta )Creating a work )RTL )NETLIST )Layout TUTORIAL is aimed at introducing a user to the CADENCE tool. It gives step by step approachto performing a RTL simulation, gate level synthesis/simulation and finally layout design usingSOCENCOUNTER sautoplaceandroute with TSMC m standard cell library. Thetutorialhowever does not discuss installation and environment setup for CADENCE . The entiretutorial is organized into five chapters beginning with connecting toVoltaserver on whichCADENCE resides.
2 It then explains RTL simulation, gate-level synthesis, post-synthesissimulation and layout design using 1 Connecting to the Volta serverThere are two ways of connecting to theVolta server on which CADENCE is installed. Connecting remotely X-Win32 orSecureShell Client can be used to establishaconnection to the client can be downloaded from SDSU collegewebsite- client installation steps are given here. X-Win32 can be installed in the same manner and aconnection established withthe Volta clientinstallation,click on the SSH client icon to invoke the pop-up paneclick on the File menutaband select Quick Connect optionto connect to theVolta thehostnameand theusernameand click and Password Enter the username and password provided to you.
3 Connecting from a school computer The second approach to connect to the VOLTA server is to use the LINUX machines available to the Linux machinesusing the username and password provided to you. Invoke the command prompt. Verify ifaconnection has been established with the Voltaserver. Ifthe connection is not established,executethe following command atthe prompt, X the command login to the 2 Creating a work directoryThe first step in using CADENCE effectively is to create a work directory/folder. A workdirectory enables the user to organizethecode files. The user can create folder for every projectthat is implemented on CADENCE .
4 The following steps need to be followed in order tocreate awork folder, Ensure that a folder calledcadenceis available in your home directory. Every user ontheVolta server is assigned a home directory to which he/she has exclusive access. The homedirectory generally has the same name as the Username. Following commands could be usedto verify the presence of CADENCE directory/folder in the home directory.>> cd /home/student/<Enter username>>> lsSee if the CADENCE folder is present in this folder. Change to CADENCE directory using the command>>cd CADENCE This directory should have the following three files for CADENCE to compile verilog fileswithout any errors.
5 The files are, a script thatbgx_shelluses in order to compile theuser created Verilogfiles. contains module path and all other details necessary for6generating an object file. The remaining two files contain delay information forTSMC would be used in our these files are not present then they need to be copied into CADENCE folder. Once the CADENCE folder is created and all the necessary files copied, the work folder has tobe created in the CADENCE directory. The work directory will house all theVerilog files andtest benches. The following command can be used to do the same.
6 >>mkdir counter// this creates a folder named counter>>cd counter// Changes the directory to counter. Now create a folder namedencounterin the work folder will house files thatare necessary for proper execution of the SOCENCOUNTER tool. TheSOCENCOUNTER tool could be used to generate the layout for compiled/synthesizedVerilog/netlist to be executed for creating the encounter folder,>>mkdirencounter>>cd encounterNote Before executing these commands ensure that you are in the work directory(whichis Counter in the current example).7 Copy the files1) 2) ) 4) these folder. These filesare necessary for proper functioning of the ENCOUNTER tool and should be made availableto you before you start working with CADENCE .
7 Also copy1) 2) encounter folder. These containdelay informationand definitionof TSMC standard files are usedwhen verifying the synthesized code using theVerilog-XL compiler. Copy both theVerilog as well as the testbench file into the encounter folder. You could use aSSH client to copy the already created files or create newVerilog and testbench files using aVI Steps to Createverilog and testbench files are beyond the scope of this 3 RTLS imulation using verilog -XL compilerA good design practice dictates that a designer first carry out RTL simulation in order to validatethe design and then eventually move over to gate level synthesis.
8 A RTL simulation lets us knowif the behavior of the component isas order to carry out RTL simulation we can use either1) verilog -XL )NCVERILOG and NCSIM(simvision).This TUTORIAL describes the use ofVerilog-XLcompiler of CADENCE in order to carry out RTLsimulation. The following command has tobe executed to invoke the compiler,>> verilog user has to pay attention when specifying the files names. The files have to be specified in aparticular order such that the lower-level modulesarecompiledbeforethe higher-level testbench would be the last item tobecompiled. Upon execution of the above statement thesimulation results are displayed on the terminal.
9 (For the simulation results to be displayed on theterminal the designer has to include display or monitor tasks in the testbench).9 GATE LEVEL SYNTHESISGate level synthesis involves implementing the behavior of the circuit (describedby a Verilogmodel) using standard gates. In gate level synthesis,theVerilog file is synthesized intoa netlistfile whichincludesstandard gatesand their delays. In any design process the simulation of thisgate-level netlist will eventuallyshowsthe success or failure of the design. Along with the netlistfile the synthesis script also generates timing-report, area report and power report.
10 The timingreport is a critical piece of information. It gives details about critical path whichindicateswhether the circuit meets the timing/frequency to carry out gate level synthesis, is used to generate the gate level netlist. The following changesneed to be made to the script in order to generate the gate level netlist file(which will have a .vhextension) and .sdc file which would contain the timing informationfor standard gates present inthe netlist file. The .vh and the .sdc files are eventually used bySOCENCOUNTER to generatethe layout. Specify theVerilog file containing the definition of the top-level module.
