Example: biology
Search results with tag "Axi uart"
AXI UART 16550 v2 - Xilinx
www.xilinx.comAXI UART 16550 v2.0 6 PG143 October 5, 2016 www.xilinx.com Chapter 1: Overview The AXI UART 16550 modules are described in these sections: • AXI Interface: This block implements the AXI4-Lite slave interface for register access and data transfer.
AXI UART Lite v2 - Xilinx
www.xilinx.comThe AXI UART Lite resource ut ilization for various parameter co mbinations measured with a 7 series device. Note: Resource numbers for UltraScale architecture-based devices and Zynq devices are expected to be similar to 7 series device numbers. Port Descriptions The AXI UART Lite I/O signals are listed and described in Table 2-3.