Transcription of 0 R XC9572XL High Performance CPLD - All …
{{id}} {{{paragraph}}}
Example: marketing
0 R XC9572XL High Performance CPLD - All …
DS057 ( ) April 3, Specification 2006 xilinx , Inc. All rights reserved. All xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without 5 ns pin-to-pin logic delays System frequency up to 178 MHz 72 macrocells with 1,600 usable gates Available in small footprint packages-44-pin PLCC (34 user I/O pins)-44-pin VQFP (34 user I/O pins)-48-pin CSP (38 user I/O pins)-64-pin VQFP (52 user I/O pins)-100-pin TQFP (72 user I/O pins)-Pb-free available for all packages Optimized for high- Performance systems-Low power operation-5V tolerant I/O pins accept 5V, , and or output capability-Advanced micron feature size CMOS Fast FLASH technology Advanced system features-In-system programmable-Superior pin-locking and routability with Fast CONNECT II switch matrix-Extra wide 54-input Function Blocks-Up to 90 product-terms per macrocell with individual product-term allocation-Local clock inversion with three global and one product-term clocks-Indivi
XC9572XL High Performance CPLD DS057 (v2.0) April 3, 2007 www.xilinx.com 3 Product Specification R Absolute Maximum Ratings(2) Recommended Operation Conditions Quality and Reliability Characteristics
Tags:
Information
Domain:
Source:
Link to this page:
Please notify us if you found a problem with this document: