Transcription of 1. Verilog HDL
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1. Verilog HDL
(2008)11. Verilog HDL 1. Verilog HDL (2008)2 Verilog HDL qVerilog HDLv1983 Gateway Design Automation HiLo C v1991 Cadence Design Systems Open Verilog International (OVI) Verilog HDL v1993 IEEE Working Group v1995 12 IEEE Std. 1364-1995 v2001 IEEE Std. 1364-2001 vVerilog HDL SystemVerilog IEEE (2008) Verilog HDL C qC v v (procedural) vif~else , case , for loop v : (&, |, ^..), (+, -, * /..), (<, >=, ==, ..)qHDL v (concurrent) v (parallel)v (abstraction) 3 (2008)HDL 3 Modelingq (Structural) v , v (netlist) q (dataflow) v v q (behavioral) vif~else, case, while, for v 4 (2008) Verilog q (simulation) : full setq (synthesis) : subsetqLibrary : system q (documentation) : fullset5 Verilog HDLassign,if~else,case, foralways specify$widthtableSimulation, Libraryinitial,$finish$ (2008) 6 SpecificationDesign EntryHigh levelSynthesisGate levelSynthesisTechnology MappingFunctional(RTL)SimulationBehavior alSimulationGate levelSimulationTimingSimulationHigh levelAbstractionLow levelAbstraction.
Ver1.0 (2008)1 1. Verilog HDL 문법 디지털시스템설계및실습 한국기술교육대학교전기전자통신공학부
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