1. Verilog HDL - KOREATECH

(2008)11. Verilog HDL 1. Verilog HDL (2008)2 Verilog HDL qVerilog HDLv1983 Gateway Design Automation HiLo C v1991 Cadence Design Systems Open Verilog International (OVI) Verilog HDL v1993 IEEE Working Group v1995 12 IEEE Std. 1364-1995 v2001 IEEE Std. 1364-2001 vVerilog HDL SystemVerilog IEEE (2008) Verilog HDL C qC v v (procedural) vif~else , case , for loop v : (&, |, ^..), (+, -, * /..), (<, >=, ==, ..)qHDL v (concurrent) v (parallel)v (abstraction) 3 (2008)HDL 3 Modelingq (Structural) v , v (netlist) q (dataflow) v v q (behavioral) vif~else, case, while, for v 4 (2008) Verilog q (simulation) : full setq (synthesis) : subsetqLibrary : system q (documentation) : fullset5 Verilog HDLassign,if~else,case, foralways specify$widthtableSimulation, Libraryinitial,$finish$ (2008) 6

Verilog HDL의역사 qVerilog HDL v1983년Gateway Design Automation사에서하드웨어기술언어인 HiLo와C 언어의특징을기반으로개발 v1991년Cadence Design Systems가Open Verilog International (OVI)라는조직을구성하고Verilog HDL을공개 v1993년IEEE Working Group이구성되어표준화작업을진행

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