1. Verilog HDL - KOREATECH

1 (2008)11. Verilog HDL 1. Verilog HDL (2008)2 Verilog HDL qVerilog HDLv1983 Gateway Design Automation HiLo C v1991 Cadence Design Systems Open Verilog International (OVI) Verilog HDL v1993 IEEE Working Group v1995 12 IEEE Std. 1364-1995 v2001 IEEE Std. 1364-2001 vVerilog HDL SystemVerilog IEEE (2008) Verilog HDL C qC v v (procedural) vif~else , case , for loop v : (&, |, ^..), (+, -, * /..), (<, >=, ==, ..)qHDL v (concurrent) v (parallel)v (abstraction) 3 (2008)HDL 3 Modelingq (Structural) v , v (netlist) q (dataflow) v v q (behavioral) vif~else, case, while, for v 4 (2008) Verilog q (simulation) : full setq (synthesis) : subsetqLibrary : system q (documentation).

2 Fullset5 Verilog HDLassign,if~else,case, foralways specify$widthtableSimulation, Libraryinitial,$finish$ (2008) 6 SpecificationDesign EntryHigh levelSynthesisGate levelSynthesisTechnology MappingFunctional(RTL)SimulationBehavior alSimulationGate levelSimulationTimingSimulationHigh levelAbstractionLow levelAbstraction : , , , , ..C, System C, SystemVerilog : Verilog , VHDL RTL : , Adder, , ALU, .. Verilog , VHDL ,: , Verilog , VHDL : SoC, ASIC, FPGA. , EDIF, (2008) Verilog (2008) (Half Adder) x yco s 0 00 11 01 10 00 10 11 08 S = x xoryco = xy moduleHA(x,y,co,s);inputx;inputy;outputc o,s;HAsxycomodule nameoutput (2008) (Half Adder) q 9 (2008) (Half Adder) q 10 (x,y,co,s);inputx;inputy;outputco,s;// , andU1(co,x,y);// xorU2(s,x,y); (x,y,co,s);inputx;inputy;outputco,s;// , assigns=x^y;//bitwiseXOR assignco=x&y;//bitwiseAND (2008) (Half Adder) q 11 (x,y,co,s);inputx;inputy;outputco,s;regc o,s;// , always@(xory)begins=x^y;//blocking co=x&y; (x,y,co,s);inputx,y;outputco,s;regco,s.

3 // , (2008) q (stimulus) 12 `timescale1ns/1ps// moduleTB_HA;regx,y;wirecout,sum;//DUTins tanceHA_bU1(.x(x),.y(y),.co(cout),.s(sum ));//inputstimulusinitialbeginx=0;y=0;#2 00;//200ns x=0;y=1;#200;//200ns x=1;y=0;#200;x=1;y=1;#200;$finish;// endendmodule (2008) Verilog q (lexical tokens)v (white space)v (comment)v (operator)v (number)v (string)v (identifier)v (keyword) (2008)14 Verilog q (white space)v (space), (tab), v v (blank) q (comment)vHDL , v ; // v ; /* ~ */ (nested) q (operator)v , 2 , 3 (2008)15 Verilog q (identifier)v v v v ; , , $, $ , v (escaped identifier).

4 \(back slash) , ( , , ) ASCII q (keyword)vVerilog v (2008)16 Verilog shiftreg_abusa_indexerror_conditionmerge _ab_bus3n$657\busa+index\-clock\**error- condition**\net1/\net2\{a,b}\a*(b+c) : : (2008) Verilog 17q (number representation)v (integer) ; 10 , 16 , 8 , 2 v : [size_constant]: 0 unsigned 10 , unsized ( , 10 ) 32 x(unknown) z(high-impedance) unsizedunsigned 'base_format: (base) (d, D, h, H, o, O, b, B) signed s S number_value: unsigned 'base_format base_format number_value [size_constant]'<base_format> <number_value> (2008)18 Verilog q (number representation)v 10 signed v unsigned v s signed s , v 2 (2 s complementary) v unsigned MSB 0 MSB x z , x z v ( ?)

5 Z v (underscore) , (readability) (2008)19 Verilog 1032 Decimal10 2 b102 Binary2103 d53 Decimal51018 o58 Octal5000001018 ha8 Hex10000010103 b5 Invalid!3 b01x3 Binary-01x12 hx12 Hex-xxxxxxxxxxxx8 b0000_00018 Binary1000000018 bx018 Binary-xxxxxx01 (32bits)8 HAD8 Hex17310101101 Number # of BitsBaseDec. (2008)20 Verilog 1250 // 10 'o765 // 8 'sHab74 // 16 'b1100_111 // 2 'bz// (32 bits)4af// illegal (hexadecimal format requires 'h)3'b110 // 3 2 , 1104'b1zx0 // 4 2 , 1zx09'O513 // 9 8 , 1_0100_10118'hef // 8 16 , 1110_1111 8'bz // 8 2 , z , zzzzzzzz6'b1 // 6 2 , 00_00016'shA // 6 16 , 00_10106'h97 // 6 16 , 01_0111, 2 12'd15 // 12 10 , 0000_0000_1111 : unsized.

6 Sized (2008)21 Verilog 8'shE0 // 1110_0000, -32 2 , // 8 hE0 -8'shE0 // -(8'1110_0000), 0010000, +32 - d100 // 232-100 = 4294967196-'sd100 // -100 = 4294967196-5 d6 // -6 5 2 , 110104'sb1010 // -612'sb0010 // 0000_0000_0010, +2 27_195_00016'b0011_0101_0001_111132'h12a b_f001 : signed : (2008)22 Verilog reg [11:0] a, b, c, d;initial begina = 'hx; // yields xxxb = 'h3x; // yields 03xc = 'hz3; // yields zz3d = 'h0z3; // yields 0z3end : MSB (2008)23 Verilog v (real) ; IEEE Std. 754-1985(IEEE standard for double-precision floating-point number) 3e4 87E-4 . : : (theEisnotcasesensitive) (2008)24 Verilog q (string)v ( ) v , v8 ASCII unsigned v reg , 8 reg [8*18:1] str1;initial beginstr1 = "Hello Verilog HDL!

7 ";end : string (2008)25 Verilog module str_test;reg[8*10:1] str1;initial beginstr1 = Hello ;$display( %s is stored as %h", str1, str1);str1 = {str1, " !!!"};$display( %s is stored as %h", str1, str1);endendmoduleHello is stored as 000000000048656c6c6fHello !!! is stored as 0048656c6c6f20212121 : string (2008)26 Verilog v (escaped character) \nNew line character\tTab character\\\character\""character\dddA character specified in 1 3 octal digits (0 d 7) (2008) Verilog (Logic Value) 01z or Zx or Xzero,low,orfalseone,high,ortruehighimpe dance(tri-statedorfloating)unknownorunin itialized27 v4 logic (2008) (Logic strength)q8 4 driving, 3 capacitive, 2 high impedance (no strength)28 strengthlevelstrength (2008)

8 Velilog Keyword29alwaysandassignautomatic beginbufbufif0bufif1casecasexcasezcell cmosconfig deassigndefaultdefparamdesign disableedgeelseendendcaseendconfig endfunctionendgenerate endmoduleendprimitiveendspecifyendtablee ndtaskeventforforceforeverforkfunctionge nerate genvar highz0highz1ififnoneinitialinstance inoutinputintegerjoinlargeliblist localparam macromodulemediummodulenandnegedgenmosno rnotnoshowcancelled notif0notif1oroutputparameterpmosposedge primitivepull0pull1pulldownpulluppulsest yle_onevent pulsestyle_ondetect rcmosrealrealtimeregreleaserepeatrnmosrp mosrtranrtranif0rtranif1scalaredsignedsh owcancelled smallspecifyspecparamstrengthstrong0stro ng1supply0supply1tabletasktimetrantranif 0tranif1tritri0tri1triandtriortriregunsi gneduse (2008)30 Verilog HDL module module_name(port_list);endmodule always, initial function, task assign function, task port reg wire parameter No SemicolonSemicolon (module) , design entity (2008) (definition)// (ImplicitInternalConnection)modulemodule _name(port_name,port_name.)

9 ;module_itemsendmodule31 // (ExplicitInternalConnection)modulemodule _name(.port_name(signal_name),.port_name (signal_name),..); (2008) (definition)qmoduleitemsvmodule_port_dec larationsvdata_type_declarationsvmodule_ instancesvprimitive_instancesvprocedural _blocksvcontinuous_assignmentsvtask_defi nitionsvfunction_definitions32 (2008) (definition) 33 , moduleex1(a1,b1,out1);input[3:0]a1,b1;ou tputout1;assignout1=(a1>=b1);// //2inputMUXwith2bitwidthsmoduleex2(input wire[1:0]i0,i1,inputwiresel,outputwire[1 :0]out2);wiret0,t1;assignout2={t1,t0};// concatenationassignt1=sel?i1[1]:i0[1];as signt0=sel?i1[0]:i0[0]; (2008) (definition) // moduleexp_port1(.)

10 A(n1),.b(n2));//n1,n2 //a,b moduleexp_port2(.a({b,c}),d,.f(g,h[2])); //b,c,d,g,h[2] //a,d,f moduleexp_port3({a,b},.c(d))//a,b,d //{a,b},c 34 (2008) (port declaration)q q vinput: (scalar) (vector) voutput: (scalar) (vector) vinout: (scalar) (vector) 35 port_directiondata_typesigned[port_size] port_name,port_name,..; (2008) // inputa1,a2,en;//3 1 inputsigned[7:0]a,b;//2 8 signed outputregsigned[16:0]res;// signed outputreg[11:0]cnt1;//littleendian inout[0:15]data_bus;//bigendian input[15:12]addr;//msb:lsb parameterBW=32;input[BW-1:0]addr;// parameterSIZE = 4096; input[log2(SIZE)-1:0] addr; // 36 (2008)37 Verilog HDL wire, reginputwirewireinoutwireoutputwire, regModule_instance_Awirewire, regModule_instance_Bwire,regwirewirewire wirewirealwaysbegin.