Transcription of © Copyright 2015 2018 Xilinx
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Copyright 2015 2020 Xilinx Copyright 2015 2020 XilinxPage (Tj = 0 C to 110 C).For more details, see the Ordering Information section in DS890, UltraScale Architecture and Product achievable performance is device and package dependent; consult the associated data sheet for full part number details, see the Ordering Information section in DS890, UltraScale Architecture and Product NameKU3 PKU5 PKU9 PKU11 PKU13 PKU15 PKU19 PLogicSystem Logic Cells (K)3564756006537471,1431,843 CLB Flip-Flops (K)3254345485976831,0451,685 CLB LUTs (K)163217274299341523842 MemoryMax. Distributed RAM (Mb) Block RAM (Mb) (Mb) MgmtTiles (CMTs)44484119 Integrated IP DSP Slices1,3681,8242,5202,9283,5281,9681,08 0 PCIE4 (PCIe Gen3 x16)1104050 PCIE4C (PCIe Gen3 x16 / Gen4 x8 /CCIX)0000003150G Interlaken0001040100G Ethernet w/ KR4 RS-FEC0102041I/OMax.
Title: UltraScale+ FPGA Product Tables and Product Selection Guide Author: Xilinx Subject: UltraScale+ FPGA Product Tables and Product Selection Guide
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