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1 Copyright 2015 2020 Xilinx Copyright 2015 2020 XilinxPage (Tj = 0 C to 110 C).For more details, see the Ordering Information section in DS890, UltraScale Architecture and Product achievable performance is device and package dependent; consult the associated data sheet for full part number details, see the Ordering Information section in DS890, UltraScale Architecture and Product NameKU3 PKU5 PKU9 PKU11 PKU13 PKU15 PKU19 PLogicSystem Logic Cells (K)3564756006537471,1431,843 CLB Flip-Flops (K)3254345485976831,0451,685 CLB LUTs (K)163217274299341523842 MemoryMax. Distributed RAM (Mb) Block RAM (Mb) (Mb) MgmtTiles (CMTs)44484119 Integrated IP DSP Slices1,3681,8242,5202,9283,5281,9681,08 0 PCIE4 (PCIe Gen3 x16)1104050 PCIE4C (PCIe Gen3 x16 / Gen4 x8 /CCIX)0000003150G Interlaken0001040100G Ethernet w/ KR4 RS-FEC0102041I/OMax.

2 Single-Ended HD I/Os96969696969672 Max. Single-Ended HP I/Os208208208416208572468 GTH Transceivers00283228440 GTY Transceivers161602003232 Speed GradesExtended(1)-1 -2 -2L -3-1 -2 -2L -3-1 -2 -2L -3-1 -2 -2L -3-1 -2 -2L -3-1 -2 -2L -3-1 -2 -2L -3 Industrial-1 -1L -2-1 -1L -2-1 -1L -2-1 -1L -2-1 -1L -2-1 -1L -2-1 -1L -2 Footprint(2, 3)Dimensions (mm)HD I/O, HP I/O, GTH , GTY compatible with 20nm UltraScale Devices with same footprint identifierB784(4)23x23(5)96, 208, 0, 1696, 208, 0, 16A676(4)27x2748, 208, 0,1648, 208, 0, 16B67627x2772, 208, 0, 1672, 208, 0, 16D900(4)31x3196, 208,0, 1696, 208, 0, 1696, 312, 16, 0E90031x3196, 208, 28, 096, 208, 28, 0A1156(4)35x3548, 416, 20, 848, 468, 20, 8E151740x4096, 416, 32, 2096, 416, 32, , 416, 44, , 572, 32, , 468, 0, , 468, 0, 32 Kintex UltraScale+ transceiver line rates are package limited: B784 to Gb/s; A676, D900, and A1156 to Gb/s.

3 Refer to data sheet for details. B784 package is only offered in ball pitch. All other packages are ball pitch. Copyright 2015 2020 XilinxPage 3 Virtex UltraScale+ FPGAsFoundation58G PAM4 DeviceNameVU3 PVU5 PVU7 PVU9 PVU11 PVU13 PVU19 PVU23 PVU27 PVU29 PSystem Logic Cells (K)8621,3141,7242,5862,8353,7808,9382,25 22,8353,780 CLB Flip-Flops (K)7881,2011,5762,3642,5923,4568,1722,05 92,5923,456 CLB LUTs (K)3946017881,1821,2961,7284,0861,0301,2 961,728 Max. (Mb) Block RAM (Mb) (Mb) Slices2,280 3,474 4,560 6,840 9,21612,2883,8401,3209,21612,288 Peak INT8 DSP (TOP/s) Gen3 x162 4 4 6 3 4 0011 PCIeGen3 x16/Gen4 x8 / CCIX(1) 84 150G Interlaken3 4 69680088100G Ethernet w/ KR4 RS-FEC3469912021515 Max.

4 Single-Ended HP I/Os520 832 8328326248321,976572676676 Max. Single-Ended HD I/Os000000967200 GTY Transceivers4080801209612880343232 GTM 58Gb/s PAM4 Transceivers 44848100G / 50G KP4 FEC 2 / 424 / 4824 / 48 Extended(2)-1 -2 -2L -3-1 -2 -2L -3-1 -2 -2L -3-1 -2 -2L -3-1 -2 -2L -3-1 -2 -2L -3-1 -2 -1 -2 -2L -3-1 -2 -2L -3-1 -2 -2L -3 Industrial-1 -2-1 -2-1 -2-1 -2-1 -2-1 -2 -1, -2-1 -2-1 -2 Footprint(3,4, 5)Dim. (mm)HP I/O, GTYHP I/O, HD I/O, GTYHP I/O,HD I/O,GTY,GTMF ootprint compatible with 20nm UltraScale Devices with same footprint identifierA136535x35364, 0, 34(8), 4C151740x40520, , 72, 34, 4F1924(6)45x45624, , 52832, 52832, (7)832, , 76702, 76702, 76572, (7)702, , 80416, 80416, 104416, (7)416, , 76572, (7)676, 76676, 16, 30676, 16, , 120448, 96448, 128448, 32, 48448, 32, 48A382465x651976, 96,48B382465x651664, 96, block operates in compatibility mode for (Gen4) operation.

5 See (Tj = 0 C to 110 C).See Ordering Information in full part number details, see DS890, UltraScale Architecture and Product packages are ball pitch. UG583, UltraScaleArchitecture PCB Design User Guide for specific migration GTY transceiver line rate in the F1924 footprint is package limited to Refer to data sheet for details. packages have the same PCB ball footprint as the packages and are footprint in quads 224-230 and 232 are limited to 16Gb/s. Copyright 2015 2020 XilinxPage 4 Virtex UltraScale+ FPGAsHBM (4GB)HBM (8GB)HBM (16GB)DeviceNameVU31 PVU33 PVU35 PVU37 PVU45 PVU47 PVU57 PSystem Logic Cells (K)9629621,9072,8521,9072,8522,852 CLB Flip-Flops (K)8798791,7432,6071,7432,6072,607 CLB LUTs (K)4404408721,3048721,3041,304 Max.

6 (Mb) Block RAM (Mb) (Mb) DRAM (GB)4888161616 HBM AXI Interfaces32323232323232 Clock MgmtTiles (CMTs)4481281212 DSP Slices2,8802,8805,9529,0245,9529,0249,02 4 Peak INT8 DSP (TOP/s) Gen3 x160012120 PCIeGen3 x16/Gen4 x8 / CCIX(1)4444444150G Interlaken0024244100G Ethernet w/ KR4 RS-FEC22585810 Max. Single-Ended HP I/Os208208416624416624624 GTY Transceivers32326496649632 GTM 58Gb/s PAM4 Transceivers 32100G / 50G KP4 FEC 16/32 Extended(2)-1 -2 -2L -3-1 -2 -2L -3-1 -2 -2L -3-1 -2 -2L -3-1 -2 -2L -3-1 -2 -2L -3-1 -2 -2L -3 Industrial Footprint(3, 4, 5, 6)Dim. (mm)HP I/O, GTYHP I/O, GTY, GTMH192445x45208, , 32416, 64416, 64H289255x55416, 64624, 96416, 64624, 96K289255x55624, 32, block operates in compatibility mode for (Gen4) operation.

7 See (Tj = 0 C to 110 C).See Ordering Information in full part number details, see DS890, UltraScale Architecture and Product packages are ball pitch. UG583, UltraScale Architecture PCB Design User Guide for specific migration compatible with 20nm UltraScale Devices with same footprint identifier. Copyright 2015 2020 XilinxUltraScale Architecture Migration body size of the VU13P device in the A2104, B2104, C2104, and D2104 packages is These packages are footprint compatible with the corresponding body size UG583, UltraScale Architecture PCB Design User Guide for important migration details.

8 UltraScale+ HBM devices migrate among each other but do not migrate to other devices. Copyright 2015 2020 XilinxPage 6 Kintex UltraScale+ FPGA Speed GradesNotes: full part number details, see the Ordering Information section in DS890, UltraScale Architecture and Product (Tj= 0 C to 110 C). For more details, see the Ordering Information section in DS890, UltraScale Architecture and Product Overview. :: available :: not offeredDevice Name(1)Speed GradeKU3 PKU5 PKU9 PKU11 PKU13 PKU15 PKU19 PExtended(2)-1 -2 -2L -3 Industrial-1 -1L -2 Copyright 2015 2020 XilinxPage 7 Virtex UltraScale+ FPGA Speed GradesDevice Name(1)Speed GradeVU3 PVU5 PVU7 PVU9 PVU11 PVU13 PVU19 PVU23 PVU27 PVU29 PVU31 PVU33 PVU35 PVU37 PVU45 PVU47 PVU57 PExtended(2)-1 -2 -2L -3 Industrial-1 -2 Notes.

9 Full part number details, see the Ordering Information section in DS890, UltraScale Architecture and Product (Tj= 0 C to 110 C). For more details, see the Ordering Information section in DS890, UltraScale Architecture and Product Overview. :: available :: not offered Copyright 2015 2020 XilinxPage 8 UltraScale+ Device Ordering InformationE = Extended (Tj = 0 C to +100 C)I = Industrial (Tj = 40 C to +100 C)Important: Verify all data in this document with the device data sheets found at valid part/package combinations, go to DS890, UltraScale Architecture and Product Overview: Device-Package Combinations and Maximum I/Os TablesF: LidL: Lid SSIB: LidlessS: Lidless StiffenerH: Overhang SSII: Overhang Lidless StiffenerV: RoHS 6/6G.

10 RoHS 6/6 w/ Exemption 15 PackageDesignatorSpeed Grade-1 = Slowest-L1 = Low Power-2 = Mid -L2 = Low Power-3 = FastestFootprintTemperature Grade(E, I)PackagePin Count-1 FLVA#EXilinx CommercialUltraScaleV: VirtexK: KintexValueIndexXCVUD enotesUltraScale+DeviceP#F: Flip-Chip ( )S: Flip-Chip ( )V: Flip-Chip( ) Copyright 2015 2020 XilinxDS890, UltraScale Architecture and Product OverviewDS922, Kintex UltraScale+ FPGAs Data Sheet: DC and AC Switching CharacteristicsDS923, Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching CharacteristicsUG570, UltraScale Architecture Configuration User GuideUG571, UltraScale Architecture SelectIO Resources User GuideUG572, UltraScale Architecture Clocking Resources User GuideUG573, UltraScale Architecture Memory Resources User GuideUG574, UltraScale Architecture Configurable Logic Block User GuideUG575,UltraScale and UltraScale+ FPGAs Packaging and Pinouts Product SpecificationUG576, UltraScale Architecture GTH Transceivers User GuideUG578, UltraScale Architecture GTY Transceivers User GuideUG579, UltraScale Architecture DSP Slice User GuideUG580.