Transcription of 3D IC-Package-Board Co-Analysis Using 3D EM Simulation …
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3D IC-Package-Board Co-Analysis Using 3D EM Simulation …
3D IC-Package-Board Co-Analysis Using 3D EM Simulation for mobile applications Darryl Kostka*, Taigon Song#, Sung Kyu Lim# * CST of America # School of Electrical and Computer Engineering 1400 Fashion Island Blvd., suite 300, San Mateo, CA 94404 Georgia Institute of Technology, Atlanta, GA 30332 Abstract 3D IC based systems necessitate a chip-package co-design approach since the TSV response in the chip stack can propagate into the package. In this work, we demonstrate a chip-interposer Co-Analysis methodology that includes the 3D CAD model of the 3D IC and compare this to the conventional analysis techniques. Our findings demonstrate that the coupling between signal TSV s in the chip stack has a significant impact on the overall channel response and needs to be carefully modeled in order to obtain accurate results.
in the power delivery network (PDN) as well. It has been demonstrated that the crosstalk waveform exhibits a distinct ... 3D IC-Package-Board Co-Analysis Using 3D EM Simulation for Mobile Applications
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