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4 VERIFICATION PLAN - SystemVerilog

4 VERIFICATION plan The VERIFICATION plan is a specification for the VERIFICATION effort. It is used to define what is first-time success, how a design is verified, and which testbenches are written1. This chapter addresses the description of a VERIFICATION plan for the UART specified in chapter 2 and with the implementation plan defined in chapter 3. The VERIFICATION plan makes use of suggestions written in Writing Testbenches and Reuse Methodology Manual2. The types of VERIFICATION tests can comprise of compliance, corner case, random, real code, and regression testing. In addition to the VERIFICATION plan , this chapter provides a discussion on VERIFICATION languages, general VERIFICATION requirements for components, and the rationale for the selection of VHDL for this book.

4.1 METHODOLOGIES 4.1.1 What is a Verification Plan A verification plan is a document that defines the following: 1. Tests or transactions applied to the design . These tests are used to verify the design functional correctness as specified in the requirement specification. This includes tests at the top-level of the design as well as

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