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AN3940, Hardware and Layout Design Considerations for …

Freescale SemiconductorApplication Note 2010-2013 Freescale Semiconductor, Inc. All rights reserved. This document provides general Hardware and Layout Considerations and guidelines for Hardware engineers implementing a DDR3 memory rules and recommendations in this document serve as an initial baseline for board designers to begin their specific implementations, such as fly-by memory is strongly recommended that the board designer verifies that all aspects, such as signal integrity, electrical timings, and so on, are addressed by using simulation models before board Number: AN3940 Rev. 6, 11/2013 Contents1. DDR3 designer checklist .. 22. Selecting termination resistors .. 93. Avoiding VREF noise problems .. 94. Calculating VTT current.

Hardware and Layout Design Considerations for DDR3 SDRAM Memory Interfaces, Rev. 6 Freescale Semiconductor 5 DDR3 designer checklist 30. Note: Some product implementations may support only the single-ended version of the strobe. † Match all segment lengths between differential pairs along the entire length of the pair.

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