Transcription of AN5097, Hardware and Layout Design Considerations for …
{{id}} {{{paragraph}}}
Example: bankruptcy
AN5097, Hardware and Layout Design Considerations for …
1 About this documentThis document provides general Hardware and layoutconsiderations and guidelines for Hardware engineersimplementing a DDR4 memory rules and recommendations in this document serve as aninitial baseline for board designers to begin their specificimplementations, such as fly-by memory is strongly recommended that the boarddesigner verifies that all aspects, such assignal integrity, electrical timings, and soon, are addressed by using simulationmodels before board resourcesThe following documentation may provide additional,important information: The DDR chapter of the applicable device referencemanual Micron s website: JEDEC s website: (a goodexample is DDR4 SDRAM Specification)NXP SemiconductorsDocument Number: AN5097 Application NoteRev. 1, 07/2016 Hardware and Layout DesignConsiderations for DDR4 SDRAMM emory InterfacesContents1 About this 12 Recommended 13 DDR4 Design 24 Selecting termination 95 Avoiding VREF noise VTT 97 Layout guidelines for DDR 108 Using simulation 159 Revision 16 ALS1088A DDR Layout routing 17 BDRAM reset signal 233 DDR4 Design checklistTable 1.
pair. Trace match the MDQS/MDQS pair to be within +/-5 mils. • Maintain constant line impedance along the routing path by maintaining the required line width and trace separation for the given stackup. • Avoid routing differential pairs adjacent to noisy signal lines or high-speed switching devices such as clock chips.
Loading..
Tags:
Information
Domain:
Source:
Link to this page:
Please notify us if you found a problem with this document: