Transcription of Aurora 64B/66B v11
{{id}} {{{paragraph}}}
Example: tourism industry
Aurora 64B/66B v11
Aurora 64B/66B LogiCORE IP Product Guide Vivado Design Suite PG074 April 4, 2018. Table of Contents IP Facts Chapter 1: Overview Applications .. 6. Unsupported Features.. 7. Licensing and Ordering .. 7. Chapter 2: Product Specification Performance.. 9. Resource Utilization.. 11. Port Descriptions .. 11. Chapter 3: Designing with the Core General Design Guidelines .. 61. Clocking.. 62. Reset and Power Down .. 66. Shared Logic .. 73. Using CRC .. 75. Hot Plug Logic.. 75. Clock Compensation Logic.. 76. Using Little Endian Support .. 77. Chapter 4: Design Flow Steps Customizing and Generating the Core .. 78. Constraining the Core .. 95. Simulation .. 99. Synthesis and Implementation .. 100. Chapter 5: Example Design Directory and File Contents.. 101. Quick Start Example Design .. 101. Detailed Example Design.. 103. Aurora 64B/66B Send Feedback 2.
transceivers in applicable UltraScale+, UltraScale™, Zynq®-7000, Virtex®-7, and Kintex®-7 devices. A single instance of Aurora 64B/66B core can use up to 16 valid consecutive lanes on GTX,GTH or GTY transceivers running at any supported line rate to provide a low-cost, general-purpose, data channel with throughput from 500 Mb/s to over ...
Loading..
Tags:
Information
Domain:
Source:
Link to this page:
Please notify us if you found a problem with this document: