Aurora 64B/66B v11

1 Aurora 64B/66B LogiCORE IP Product Guide Vivado Design Suite PG074 April 4, 2018. Table of Contents IP Facts Chapter 1: Overview Applications .. 6. Unsupported Features.. 7. Licensing and Ordering .. 7. Chapter 2: Product Specification Performance.. 9. Resource Utilization.. 11. Port Descriptions .. 11. Chapter 3: Designing with the Core General Design Guidelines .. 61. Clocking.. 62. Reset and Power Down .. 66. Shared Logic .. 73. Using CRC .. 75. Hot Plug Logic.. 75. Clock Compensation Logic.. 76. Using Little Endian Support .. 77. Chapter 4: Design Flow Steps Customizing and Generating the Core .. 78. Constraining the Core .. 95. Simulation .. 99. Synthesis and Implementation .. 100. Chapter 5: Example Design Directory and File Contents.. 101. Quick Start Example Design .. 101. Detailed Example Design.. 103. Aurora 64B/66B Send Feedback 2.

2 PG074 April 4, 2018. Using Vivado Lab Tools .. 106. Implementing the Example Design .. 106. Hardware Reset FSM in the Example Design .. 106. Chapter 6: Test Bench Appendix A: Verification, Compliance, and Interoperability Appendix B: Upgrading Device Migration .. 113. Upgrading in the Vivado Design Suite .. 114. Migrating Legacy (LocalLink based) Aurora 64B/66B Cores to the AXI4-Stream Aurora 64B/66B Core 116. Appendix C: Debugging Finding Help on .. 123. Vivado Design Suite Debug Feature .. 125. Simulation Debug.. 125. Hardware Debug .. 127. Design Bring-Up on the KC705 Evaluation Board .. 133. Interface Debug .. 133. Appendix D: Generating a GT Wrapper File from the transceiver Wizard Appendix E: Additional Resources and Legal Notices Xilinx Resources .. 135. Documentation Navigator and Design Hubs .. 135. References .. 135. Revision History.

3 136. Please Read: Important Legal Notices .. 141. Aurora 64B/66B Send Feedback 3. PG074 April 4, 2018. IP Facts Introduction LogiCORE IP Facts Table Core Specifics The Xilinx LogiCORE IP Aurora 64B/66B core UltraScale+ , is a scalable, lightweight, high data rate, Supported UltraScale (2), Device link-layer protocol for high-speed serial Family(1). Zynq -7000 All Programmable SoC. communication. The protocol is open and can Virtex-7(3), Kintex-7(3). be implemented using Xilinx device Supported User AXI4-Stream technology. Interfaces The Vivado Design Suite produces source Resources (4) Performance and Resource Utilization web page code for Aurora 64B/66B cores. The cores can Provided with Core be simplex or full-duplex, and feature one of Design Files Verilog two simple user interfaces and optional flow Example Verilog(5). control. Design Test Bench Verilog Features Constraints File Xilinx Design Constraints (XDC).

4 General-purpose data channels with Simulation Source HDL with SecureIP transceiver simulation throughput range from 500 Mb/s to over Model models 400 Gb/s Supported N/A. Supports up to 16 consecutively bonded 7 S/W Driver series GTX/GTH, UltraScale GTH/GTY or Tested Design Flows(6). UltraScale+ GTH/GTY transceivers The GT subcore is also available outside the Design Vivado Design Suite Entry Aurora core For supported simulators, see the Aurora 64B/66B protocol specification Simulation Xilinx Design Tools: Release Notes Guide. compliant ( 64B/66B encoding). Synthesis Vivado Synthesis Low resource cost with very low (3%). transmission overhead Support Easy-to-use AXI4-Stream based framing Provided by Xilinx at the Xilinx Support web page and flow control interfaces Notes: Automatically initializes and maintains the 1. For a complete list of supported devices and configurations, channel see the Vivado IP catalog and associated FPGA Datasheets.

5 Full-duplex or simplex operation 2. For more information, see the Virtex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics (DS893) [Ref 1]. 32-bit Cyclic Redundancy Check (CRC) for and Kintex UltraScale FPGAs Data Sheet: DC and AC. user data Switching Characteristics (DS892) [Ref 2] Kintex and Virtex Added support for the Simplex Auto Link UltraScale+ FPGAs Data Sheets: DC and AC Switching Recovery feature Characteristics (DS922)[Ref 28] and (DS923)[Ref 29]. Supports RX polarity inversion 3. For more information, see the 7 Series FPGAs Overview (DS180) [Ref 3]. and the UltraScale Architecture and Product Big endian/little endian AXI4-Stream user Overview (DS890) [Ref 4]. interface 4. For more complete performance data, see Performance, Fully compliant AXI4-Lite DRP interface page 9. 5. The IP core is delivered as Verilog source code.

6 A. Configurable DRP, INIT clock mixed-language simulator is required for example design Single-ended or differential clocking simulation because of subcore dependencies. options for GTREFCLK and core INIT_CLK 6. For the supported versions of the tools, see the Xilinx Design Tools: Release Notes Guide. Aurora 64B/66B Send Feedback 4. PG074 April 4, 2018 Product Specification Chapter 1. Overview This product guide describes the function and operation of the LogiCORE IP Aurora 64B/66B core and provides information about designing, customizing, and implementing the core. Aurora 64B/66B is a lightweight, serial communications protocol for multi-gigabit links (Figure 1-1). It is used to transfer data between devices using one or many GTX, GTH or GTY. transceivers. Connections can be full-duplex (data in both directions) or simplex (data in either one of the directions).

7 The Aurora 64B/66B core supports the AMBA protocol AXI4-Stream user interface. It implements the Aurora 64B/66B protocol using the high-speed serial GTX, GTH or GTY. transceivers in applicable UltraScale+, UltraScale , Zynq -7000, Virtex -7, and Kintex -7. devices. A single instance of Aurora 64B/66B core can use up to 16 valid consecutive lanes on GTX,GTH or GTY transceivers running at any supported line rate to provide a low-cost, general-purpose, data channel with throughput from 500 Mb/s to over 400 Gb/s. Aurora 64B/66B cores are verified for protocol compliance using an array of automated simulation tests. X-Ref Target - Figure 1-1. Aurora Channel Partners Aurora Aurora Lane 1 Channel User User Interface Aurora Aurora Interface User User 64B/66B 64B/66B . Application Application Core Core Aurora Lane n User Data 64B/66B User Data Encoded Data X13011.

8 Figure 1-1: Aurora 64B/66B Channel Overview Aurora 64B/66B Send Feedback 5. PG074 April 4, 2018. Chapter 1: Overview Aurora 64B/66B cores automatically initialize a channel when they are connected to an Aurora 64B/66B channel partner. After initialization, applications can pass data across the channel as frames or streams of data. Aurora 64B/66B frames can be of any size, and can be interrupted any time by high priority requests. Gaps between valid data bytes are automatically filled with idles to maintain lock and prevent excessive electromagnetic interference. Flow control is optional in Aurora 64B/66B , and can be used to throttle the link partner transmit data rate, or to send brief, high-priority messages through the channel. Streams are implemented in Aurora 64B/66B as a single, unending frame. Whenever data is not being transmitted, idles are transmitted to keep the link alive.

9 Excessive bit errors, disconnections, or equipment failures cause the core to reset and attempt to initialize a new channel. The Aurora 64B/66B core can support a maximum of two symbols skew in the receipt of a multi-lane channel. The Aurora 64B/66B protocol uses 64B/66B encoding. The 64B/66B encoding offers theoretical improved performance because of its very low (3%). transmission overhead, compared to 25% overhead for 8B/10B encoding. RECOMMENDED: 1. Although the Aurora 64B/66B core is a fully-verified solution, the challenge associated with implementing a complete design varies depending on the configuration and functionality of the application. For best results, prior experience in building high-performance, pipelined FPGA designs using Xilinx implementation tools and Xilinx Design Constraints (XDC) user constraints files is recommended.

10 2. Consult the PCB design requirements information in the UltraScale FPGAs GTH Transceivers User Guide (UG576) [Ref 5], UltraScale FPGAs GTY Transceivers User Guide (UG578) [Ref 6], and 7 Series FPGAs GTX/GTH Transceivers User Guide (UG476) [Ref 7]. Contact your local Xilinx representative for a closer review and estimation for your specific requirements. Applications Aurora 64B/66B cores can be used in a wide variety of applications because of their low resource cost, scalable throughput, and flexible data interface. Examples of Aurora 64B/66B . core applications include: Chip-to-chip links: Replacing parallel connections between chips with high-speed serial connections can significantly reduce the number of traces and layers required on a PCB. Board-to-board and backplane links: Aurora 64B/66B uses standard 64B/66B . encoding, which is the preferred encoding scheme for 10 Gigabit Ethernet, making it compatible with many existing hardware standards for cables and backplanes.