Transcription of AXI DMA v7 - Xilinx
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AXI DMA v7 - Xilinx
AXI DMA LogiCORE IP Product Guide Vivado Design Suite PG021 June 14, 2019. Table of Contents IP Facts Chapter 1: Overview Feature Summary.. 6. Applications .. 7. Licensing and Ordering .. 7. Chapter 2: Product Specification Performance.. 8. Resource Utilization.. 10. Port Descriptions .. 10. Register Space .. 11. Scatter Gather Descriptor .. 38. Multichannel DMA Support .. 56. Chapter 3: Designing with the Core Typical System Interconnect .. 68. Clocking.. 69. Resets .. 70. Programming Sequence.. 70. Chapter 4: Design Flow Steps Customizing and Generating the Core .. 75. Constraining the Core .. 83. Simulation .. 84. Synthesis and Implementation .. 84. Chapter 5: Example Design Implementing the Example Design .. 87. Simulating the Example Design.. 88. Test Bench for the Example Design .. 89. LogiCORE IP AXI DMA Send Feedback 2. PG021 June 14, 2019 Appendix A: Upgrading Migrating to the Vivado Design Suite.
LogiCORE IP AXI DMA v7.1 6 PG021 June 14, 2019 www.xilinx.com Chapter 1:Overview Primary high-speed DMA data movement between system memory and stream target is
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