Transcription of AXI UART Lite v2 - Xilinx - All Programmable
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AXI UART Lite v2 - Xilinx - All Programmable
AXI uart Lite IP Product GuideVivado Design SuitePG142 April 5, 2017 AXI uart Lite April 5, 2017 Table of ContentsIP FactsChapter 1: OverviewFeature Summary.. 6 Licensing and Ordering Information .. 6 chapter 2: Product SpecificationPerformance .. 7 Resource Utilization .. 8 Port Descriptions .. 8 Register Space .. 9 chapter 3: Designing with the CoreClocking.. 13 Resets .. 13 Programming Sequence.. 13 chapter 4: Design Flow StepsCustomizing and Generating the Core .. 14 Constraining the Core .. 16 Simulation .. 17 Synthesis and Implementation .. 17 chapter 5: Example DesignOverview .. 18 Implementing the Example Design .. 19 Example Design Directory Structure .. 19 Simulating the Example Design.. 20 chapter 6: Test BenchAppendix A: Migrating and UpgradingMigrating to the Vivado Design Suite.
AXI UART Lite v2.0 www.xilinx.com 5 PG142 April 5, 2017 Chapter 1 Overview The AXI UART Lite modules are shown in Figure 1-1 and described in the sections that follow.
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