Transcription of Block Memory Generator v8 - Xilinx
{{id}} {{{paragraph}}}
Example: air traffic controller
Block Memory Generator v8 - Xilinx
Block Memory Generator LogiCORE IP Product Guide Vivado Design Suite PG058 April 5, 2017. Table of Contents IP Facts Chapter 1: Overview Feature Summary.. 5. Native Block Memory Generator Feature Summary .. 7. AXI4 Interface Block Memory Generator Feature Summary .. 10. Applications .. 25. Licensing and Ordering Information .. 26. Chapter 2: Product Specification Performance.. 27. Resource Utilization.. 30. Port Descriptions .. 30. Chapter 3: Designing with the Core General Design Guidelines .. 39. UltraScale Architecture-Based Device Features.. 74. Clocking.. 77. Resets .. 77. Chapter 4: Design Flow Steps Customizing and Generating the Core .. 78. Constraining the Core .. 99. Simulation .. 99. Synthesis and Implementation .. 99. Chapter 5: Detailed Example Design Chapter 6: Test Bench Core with Native Interface.
• Supports AXI4 and AXI4-Lite interface protocols • AXI4 compliant Memory and Peripheral Slave types • Independent Read and Write Channels • Zero delay datapath • Supports registered outputs for handshake signals • INCR burst sizes up to 256 data transfers • WRAP bursts of 2, 4, 8, and 16 data beats
Loading..
Tags:
Information
Domain:
Source:
Link to this page:
Please notify us if you found a problem with this document: