Block Memory Generator v8 - Xilinx
Block Memory Generator LogiCORE IP Product Guide Vivado Design Suite PG058 April 5, 2017. Table of Contents IP Facts Chapter 1: Overview Feature Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5. Native Block Memory Generator Feature Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7. AXI4 Interface Block Memory Generator Feature Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10. Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25. Licensing and Ordering Information.
• Supports AXI4 and AXI4-Lite interface protocols • AXI4 compliant Memory and Peripheral Slave types • Independent Read and Write Channels • Zero delay datapath • Supports registered outputs for handshake signals • INCR burst sizes up to 256 data transfers • WRAP bursts of 2, 4, 8, and 16 data beats
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