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Cadence Tutorial B: Layout, DRC, Extraction, and LVS

Cadence Tutorial B: layout , DRC, extraction , and lvs Created for the MSU VLSI program by Professor A. Mason and the AMSaC lab group. Document Contents Introduction Create layout Cellview Design Rule Checking layout Parameter extraction layout vs. Schematic Comparison Introduction This document is one of a three-part Tutorial for using Cadence Custom IC Design Tools (ver: IC445) for a typical bottom-up digital circuit design flow with the AMI06 process technology and NCSU design kit. This Tutorial demonstrates how to complete the physical design ( layout ), design rule check (DRC), parameter extraction , and layout vs.

design rule check (DRC), parameter extraction, and layout vs. schematic (LVS) using the Cadence tools. These operations are performed step-by-step to complete the design of an inverter cell, began in Tutorial A, using the design rules for the AMI C5N (λ=0.3) fabrication process. Techniques and tips for using Cadence layout tools are presented.

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