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Cadence Virtuoso Tutorial - USC Viterbi

Cadence Virtuoso Tutorial version University of Southern California Last Update: Oct, 2015 EE209 Fall 2015 Table of Contents System Setup .. 3 1. Basic setup .. 3 2. Cadence setup .. 3 Basic Design Flow .. 5 1. Overall design flow .. 5 2. Create Library .. 6 3. Schematic .. 8 A. Create a cell view .. 8 B. Draw a schematic .. 9 4. Run Spectre simulation (Transient analysis) .. 16 A. Launch ADE (Analog Design Environment) L .. 16 B. Basic setup .. 17 C. Model Libraries .. 17 D. Stimuli .. 18 E. Choose a type of analysis - transient .. 20 F. Select signals to plot .. 21 G. Run simulation .. 21 H. Measurement .. 22 5. Run Spectre simulation (DC analysis) .. 25 A. Voltage Source .. 25 B. Replace Input Pin .. 26 C. Choosing Analyses .. 26 D. Run Simulation .. 27 6. 29 A. Create a layout .. 29 B. Add an instance - nmos .. 30 C. Add more instances pmos, ptap, ntap, and m1_ploy.

Remember that when you use more than one symbol in schematic, they all will have common Vdd and Gnd even if there are one Gnd and Vdd for each symbol (in the original design). To design with symbols in layout, you should make sure that all of the Vdd and Gnds are connected.

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