Transcription of Chapter 23: Wafer Level Packaging
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Chapter 23: Wafer Level Packaging
2019 Edition Chapter 23: Wafer Level Packaging We acknowledge with gratitude the use of material and figures in this Roadmap that are excerpted from original sources. Figures & tables should be re-used only with the permission of the original source. The HIR is devised and intended for technology assessment only and is without regard to any commercial considerations pertaining to individual products or equipment. October, 2019 Table of Contents HIR Version ( ) Page ii Heterogeneous Integration Roadmap Table of Contents Chapter 1: HETEROGENEOUS INTEGRATION ROADMAP: OVERVIEW .. 1 Chapter 2: HIGH PERFORMANCE COMPUTING AND DATA CENTERS .. 1 Chapter 3: THE INTERNET OF THINGS (IOT).
through-hole packaging to the advanced systems we have today using 10nm-technology-node manufacturing and a wide range of advanced packaging platforms, addressing single- and multi-die packaging. Major technology advances in semiconductors were mainly driven by Moore’s Law and scaling the technology
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