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Chapter 23: Wafer-Level Packaging (WLP) - IEEE

2021 Edition Chapter 23: Wafer-Level Packaging (WLP). For updates, visit The HIR is devised and intended for technology assessment only and is without regard to any commercial considerations pertaining to individual products or equipment. We acknowledge with gratitude the use of material and figures in this Roadmap that are excerpted from original sources. Figures and tables should be re-used only with the permission of the original source. November 2021 Table of Contents Table of Contents Chapter 1: Heterogeneous Integration Roadmap: Driving Force and Enabling Technology for Systems of the Future Chapter 2: High Performance Computing and Data Centers Chapter 3: Heterogeneous Integration for the Internet of Things (IoT). Chapter 4: Medical, Health and Wearables Chapter 5: Automotive Chapter 6: Aerospace and Defense Chapter 7: Mobile Chapter 8: Single Chip and Multi Chip Integration Chapter 9: Integrated Photonics Chapter 10: Integrated Power Electronics Chapter 11: MEMS and Sensor Integration Chapter 12: 5G, RF and Analog Mixed Signal Chapter 13: Co-Design for Heterogeneous Integration Chapter 14: Modeling and Simulation Chapter 15: Materials and Emerging Research Materials Chapter 16: Emerging Research Devices Chapter 17: Test Technology Chapter

Wafer level packaging is where a die is packaged while still in wafer form, either singly or combined with additional dies or other components such as discrete passive devices, or …

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Transcription of Chapter 23: Wafer-Level Packaging (WLP) - IEEE

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Chapter 23: Wafer Level Packaging

eps.ieee.org

last” processes were used to make top-side die connections to the pads normally located on the die underside. This process has been used by the MEMS industry to mount a logic or analog die on top of a MEMS die, or vice versa, as shown in figure 4. This became another level of WLP heterogeneous integration complexity.

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innovation in design and process technologies continue the drive to advanced nodes, Moore’s-Law economics and performance are evidently plateauing. Shown below are two graphs presented by John Hennessy at the ERI Conference in July 2018 [5]. The graph to the left shows forty years of DRAM capacity and the slowing down of

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electronics, photonics and plasmonics will be required to address these substantial new challenges in order to meet the expanding requirement for higher performance, higher reliability, increased security, lower latency and continued decrease in cost per function. The packaging of photonic integrated circuits (PICs) will face the same challenges

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Chapter 23: Wafer Level Packaging - IEEE

eps.ieee.org

The intent of this chapter is to provide a brief overview of Wafer Level Packaging (WLP), including Wafer Level Chip Scale Packaging (WLCSP) and Fan Out packaging, as a background for a …

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Demand for wafer level packaging (WLP) is not only driven by the need to shrink package size and height, simplify the supply chain and provide a lower overall cost by using the …

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