Combinational Logic Gates in CMOS

Combinational Logic Gates in CMOSR eferences:Adapted from: Digital Integrated Circuits: A Design Perspective, J. Rabaey, Prentice Hall UCBP rinciples of CMOS VLSI Design: A Systems Perspective, N. H. E. Weste, K. Eshraghian, Addison WesleyAdapted from: EE216A Lecture Notes by Prof. K. Bult UCLAC ombinational vs. Sequential LogicCombinationalSequentialStateOut = f(In)Out = f(In, State)State is related to previous inputsStored in registers, memory etcOverview Static CMOS Complementary CMOS Ratioed Logic Pass Transistor/Transmission Gate Logic Dynamic CMOS Logic Domino np-CMOSS tatic CMOS Circuit At every point in time (except during the switching transients)

• Charge sharing in dynamic logic • Incorrect clocking in dynamic logic. Complementary CMOS PUN PDN in1 in2 in3 in1 in2 in3 V DD V SS F = G NMOS only PMOS only ... 3-Input NAND gate with Parasitic Capacitors in c out in b in a C p+load C a C b C c P1 P2 P3 R n=0.5R p= C a=C b=C c=C j=0.05pF C p=3C j=0.15pF C load=2C

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  Charges, Capacitors, Sharing, Charge sharing

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