Transcription of Computer Architecture: Main Memory (Part I)
{{id}} {{{paragraph}}}
Example: bachelor of science
Computer Architecture: Main Memory (Part I)
Computer Architecture: Main Memory (Part I)Prof. Onur MutluCarnegie Mellon University(reorganized by Seth)Main MemoryMain Memory in the System3 CORE 1L2 CACHE 0 SHARED L3 CACHEDRAM INTERFACECORE 0 CORE 2 CORE 3L2 CACHE 1L2 CACHE 2L2 CACHE 3 DRAM BANKSDRAM Memory CONTROLLERI deal Memory Zero access time (latency) Infinite capacity Zero cost Infinite bandwidth (to support multiple accesses in parallel)4 The Problem Ideal Memory s requirements oppose each other Bigger is slower Bigger Takes longer to determine the location Faster is more expensive Memory technology: SRAM vs.
Memory Bank Organization and Operation Read access sequence: 1. Decode row address & drive word-lines 2. Selected bits drive bit-lines • Entire row read 3. Amplify row data 4. Decode column address & select subset of row • Send to output 5. …
Loading..
Tags:
Information
Domain:
Source:
Link to this page:
Please notify us if you found a problem with this document: