Transcription of Data Sheet: MAX 3000A Programmable Logic …
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Data Sheet: MAX 3000A Programmable Logic …
Altera Corporation 1 MAX 3000 AProgrammable LogicDevice FamilyJune 2006, ver. High performance, low cost CMOS EEPROM based Programmable Logic devices (PLDs) built on a MAX architecture (see Ta b l e 1) in-system programmability (ISP) through the built in IEEE Std. Joint Test Action Group (JTAG) interface with advanced pin-locking capability ISP circuitry compliant with IEEE Std. 1532 Built in boundary-scan test (BST) circuitry compliant with IEEE Std. Enhanced ISP features: Enhanced ISP algorithm for faster programming ISP_Done bit to ensure complete programming Pull-up resistor on I/O pins during in system programming High density PLDs ranging from 600 to 10,000 usable gates ns pin to pin Logic delays with counter frequencies of u
Altera Corporation 3 MAX 3000A Programmable Logic Device Family Data Sheet The MAX 3000A architecture supports 100 % transistor-to-transistor logic
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