Transcription of FIFO Generator v13 - Xilinx
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FIFO Generator v13 - Xilinx
FIFO Generator IP Product GuideVivado Design SuitePG057 April 5, 2017 FIFO Generator April 5, 2017 Table of ContentsIP FactsChapter 1: OverviewNative Interface FIFOs .. 5 AXI Interface FIFOs.. 6 Feature Summary.. 8 Applications .. 62 Licensing and Ordering Information .. 65 Chapter 2: Product SpecificationPerformance .. 66 Resource Utilization .. 77 Port Descriptions .. 77 Chapter 3: Designing with the CoreGeneral Design Guidelines .. 93 Initializing the FIFO Generator .. 95 FIFO Usage and Control .. 95 Clocking.. 121 Resets .. 126 Actual FIFO Depth .. 134 Latency .. 136 Special Design Considerations .. 148 Chapter 4: Design Flow StepsCustomizing and Generating the Native Core.
FIFO Generator v13.1 www.xilinx.com 5 PG057 April 5, 2017 Chapter 1 Overview The FIFO Generator core is a fully verified first-in first-out memory queue for use in any
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