Transcription of FIFO Generator v13 - Xilinx
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FIFO Generator v13 - Xilinx
FIFO Generator IP Product GuideVivado design SuitePG057 April 5, 2017 FIFO Generator April 5, 2017 Table of ContentsIP FactsChapter 1: OverviewNative Interface FIFOs .. 5 AXI Interface FIFOs.. 6 Feature Summary.. 8 Applications .. 62 Licensing and Ordering Information .. 65 Chapter 2: Product SpecificationPerformance .. 66 Resource Utilization .. 77 Port Descriptions .. 77 Chapter 3: designing with the CoreGeneral design Guidelines .. 93 Initializing the FIFO Generator .. 95 FIFO Usage and Control .. 95 Clocking.. 121 Resets.
using the IP integrator. See the Vivado Design Suite User Guide: Designing IP Subsystems using IP Integrator (UG994) [Ref 5] for more details. X-Ref Target - Figure 1-1 Figure 1-1: Native Interface FIFOs Signal Diagram dout[m:0] empty rd_en Write Clock Domain Read Clock Domain full wr_en din[n:0] almost_full Prog_full almost_empty prog_empty ...
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