FIFO Generator v13 - Xilinx

1 FIFO Generator IP Product GuideVivado design SuitePG057 April 5, 2017 FIFO Generator April 5, 2017 Table of ContentsIP FactsChapter 1: OverviewNative Interface FIFOs .. 5 AXI Interface FIFOs.. 6 Feature Summary.. 8 Applications .. 62 Licensing and Ordering Information .. 65 Chapter 2: Product SpecificationPerformance .. 66 Resource Utilization .. 77 Port Descriptions .. 77 Chapter 3: designing with the CoreGeneral design Guidelines .. 93 Initializing the FIFO Generator .. 95 FIFO Usage and Control .. 95 Clocking.. 121 Resets.

2 126 Actual FIFO Depth .. 134 Latency .. 136 Special design Considerations .. 148 Chapter 4: design Flow StepsCustomizing and Generating the Native Core .. 153 Customizing and Generating the AXI Core .. 170 Constraining the Core .. 182 Simulation .. 182 Synthesis and Implementation .. 184 Chapter 5: Detailed Example DesignImplementing the Example design .. 185 Send FeedbackFIFO Generator April 5, 2017 Simulating the Example design .. 186 Chapter 6: Test BenchTest Bench Functionality .. 187 Customizing the Demonstration Test Bench.

3 188 Messages and Warnings .. 189 Appendix A: Verification, Compliance, and InteroperabilitySimulation .. 190 Appendix B: DebuggingFinding Help on .. 191 Debug Tools .. 192 Simulation Debug.. 193 Hardware Debug .. 193 Interface Debug .. 193 Appendix C: Migrating and UpgradingMigrating to the Vivado design suite .. 195 Upgrading in the Vivado design suite .. 195 Appendix D: dout Reset Value TimingAppendix E: FIFO Generator FilesAppendix F: Supplemental InformationAppendix G: Additional Resources and Legal NoticesXilinx Resources.

4 215 References .. 215 Revision History .. 216 Please Read: Important Legal Notices .. 218 Send FeedbackFIFO Generator April 5, 2017 Product SpecificationIntroductionThe Xilinx LogiCORE IP FIFO Generator core is a fully verified first-in first-out (FIFO) memory queue for applications requiring in-order storage and retrieval. The core provides an optimized solution for all FIFO configurations and delivers maximum performance (up to 500 MHz) while utilizing minimum resources. Delivered through the Vivado design suite , you can customize the width, depth, status flags, memory type, and the write/read port aspect FIFO Generator core supports Native interface FIFOs, AXI Memory Mapped interface FIFOs and AXI4-Stream interface FIFOs.

5 Native interface FIFO cores are optimized for buffering, data width conversion and clock domain decoupling applications, providing ordered storage and Memory Mapped and AXI4-Stream interface FIFOs are derived from the Native interface FIFO. Three AXI Memory Mapped interface styles are available: AXI4, AXI3 and more details on the features of each interface, see Feature Summary in Chapter FactsLogiCORE IP Facts TableCore SpecificsSupported Device Family(1)UltraScale+ Families, UltraScale Architecture, Zynq -7000, 7 SeriesSupported user InterfacesNative, AXI4-Stream, AXI4, AXI3, AXI4-LiteResourcesPerformance and Resource Utilization web pageProvided with CoreDesign FilesEncrypted RTLE xample DesignVHDLTest BenchVHDLC onstraints FileXDCS imulation ModelVerilog Behavioral(2)Supported S/W DriverN/ATe s t e d D e s i g n F l o w s(4)

6 design EntryVivado design SuiteSimulation(3)For other supported simulators, see the XilinxDesign Tools: Release Notes SynthesisSupportProvided by Xilinx at the Xilinx Support web pageNotes: 1. For a complete listing of supported devices, see the Vivado IP Behavioral model does not model synchronization delay. See Simulation in Chapter 4 for The FIFO Generator core supports the UniSim simulation For the supported versions of the tools, see the Xilinx design Tools: Release Notes FeedbackFIFO Generator April 5, 2017 Chapter 1 OverviewThe FIFO Generator core is a fully verified first-in first-out memory queue for use in any application requiring ordered storage and retrieval, enabling high-performance and area-optimized designs.

7 The core provides an optimized solution for all FIFO configurations and delivers maximum performance (up to 500 MHz) while using minimum resources. This core supports Native interface FIFOs, AXI Memory Mapped interface FIFOs and AXI4-Stream interface FIFOs. AXI Memory Mapped and AXI4-Stream interface FIFOs are derived from the Native interface FIFO. Three AXI Memory Mapped interface styles are available: AXI4, AXI3 and core can be customized using the Vivado IP customizers in the IP catalog as a complete solution with control logic already implemented, including management of the read and write pointers and the generation of status.

8 The Memory Mapped interface FIFO and AXI4-Stream interface FIFO are referred as "AXI FIFO" throughout this Interface FIFOsThe Native interface FIFO can be customized to utilize block RAM, distributed RAM or built-in FIFO resources available in some FPGA families to create high-performance, area-optimized FPGA mode and First Word Fall Through are the two operating modes available for Native interface FeedbackFIFO Generator April 5, 2017 Chapter 1:OverviewAXI Interface FIFOsAXI interface FIFOs are derived from the Native interface FIFO, as shown in Figure 1-2.

9 Three AXI memory mapped interface styles are available: AXI4, AXI3 and AXI4-Lite. In addition to applications supported by the Native interface FIFO, AXI FIFOs can also be used in AXI System Bus and Point-to-Point high speed interface FIFOs do not support built-in FIFO and Shift Register FIFO the AXI FIFOs in the same applications supported by the Native Interface FIFO when you need to connect to other AXI functions. AXI FIFOs can be integrated into a system by using the IP integrator. See the Vivado design suite user guide : designing IP subsystems using IP Integrator (UG994) [Ref 5] for more Target - Figure 1-1 Figure 1-1:Native Interface FIFOs Signal Diagramdout[m:0]emptyrd_enWrite Clock DomainRead Clock Domainfullwr_endin[n:0]almost_fullProg_f ullalmost_emptyprog_emptyvalidunderflowp rog_empty_thresh_assertsbiterrdbiterrwr_ ackoverflowwr_data_count[p.]

10 0]prog_full_thresh_assertprog_full_thres h_negateprog_full_threshinjectsbiterrinj ectdbiterrwr_rstrstrd_rstOPTIONALMANDATO RYOPTIONAL SIDEBANDwr_clkrd_clkRead AgentWrite Agentrd_data_count[q:0]prog_empty_thresh _negateprog_empty_threshSend FeedbackFIFO Generator April 5, 2017 Chapter 1:OverviewThe AXI interface protocol uses a two-way valid and ready handshake mechanism. The information source uses the valid signal to show when valid data or control information is available on the channel. The information destination uses the ready signal to show when it can accept the data.