Transcription of High Speed USB Platform Design Guidelines - USB.org
{{id}} {{{paragraph}}}
High Speed USB Platform DesignGuidelinesRev. Speed USB Platform Design GuidelinesPage 24/26/01 REVISION HISTORYR evisionRevision "THIS SPECIFICATION [DOCUMENT] IS PROVIDED "AS IS" WITH NO WARRANTIESWHATSOEVER, INCLUDING ANY WARRANTY OF MERCHANTABILITY,NONINFRINGEMENT, FITNESS FOR ANY PARTICULAR PURPOSE, OR ANY WARRANTYOTHERWISE ARISING OUT OF ANY PROPOSAL, SPECIFICATION OR SAMPLE. Inteldisclaims all liability, including liability for infringement of any proprietary rights, relating to use ofinformation in this specification. No license, express or implied, by estoppel or otherwise, to anyintellectual property rights is granted assumes no responsibility for any errors, which may appear in this document. Intel makes nocommitment to update the information contained herein, and may make changes at any time without notice."Copyright 2000-01 Intel Corporation.
High Speed USB Platform Design Guidelines Page 7 4/26/01 Figure 3 Recommended trace spacing (mils) for the stackup given in Section 3.7 3.3 High Speed USB Termination
Domain:
Source:
Link to this page:
Please notify us if you found a problem with this document:
{{id}} {{{paragraph}}}
TWL1200, Texas Instruments, Stackup, Differential, SMSC Ethernet Physical Layer Layout, SMSC Ethernet Physical Layer Layout Guidelines, Prepreg thickness chart, Announcement, PCB Layout Checklist, Digital Signals Integrity Tutorial, Routing Rule-Based DDR, Routing Rule-Based DDR Timing Specification