Transcription of Intro to Verilog - MIT
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Intro to Verilog - MIT
Wires Theory vs Reality - Lab 1. Intro to Verilog 30-50mv voltage drop in chip Wires theory vs reality (Lab1) Wires have inductance and resistance Hardware Description Languages power Verilog supply -- structural: modules, instances noise . -- dataflow : continuous assignment .. noise during transitions -- sequential behavior: always blocks -- pitfalls Voltage drop across wires -- other useful features LC ringing after transitions Reminder: Lab #1 due by 9pm tonight Fall 2017 Lecture 3 1 Fall 2017 Lecture 3 2. Bypass (Decoupling) Capacitors The Need for HDLs Electrolytic Bypass capacitor A specification is an engineering contract that lists all the goals Capacitor 10uf typical for a project: Provides additional filtering from main goals include area, power, throughput, latency, functionality, test power supply coverage, costs (NREs and piece costs), Helps you figure out Used as local energy when you're done and how to make engineering tradeoffs.
chooses what architecture is used for a given instance of an entity. Design is composed of modules. Behavioral, dataflow and structural modeling. Synthesizable subset... Behavioral, dataflow and structural modeling. Synthesizable subset... Harder to learn and use, not technology-specific, DoD mandate Easy to learn and use, fast
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