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Intro to Verilog - MIT

Wires Theory vs Reality - Lab 1. Intro to Verilog 30-50mv voltage drop in chip Wires theory vs reality (Lab1) Wires have inductance and resistance Hardware Description Languages power Verilog supply -- structural: modules, instances noise . -- dataflow: continuous assignment .. noise during transitions -- sequential behavior: always blocks -- pitfalls Voltage drop across wires -- other useful features LC ringing after transitions Reminder: Lab #1 due by 9pm tonight Fall 2017 Lecture 3 1 Fall 2017 Lecture 3 2. Bypass (Decoupling) Capacitors The Need for HDLs Electrolytic Bypass capacitor A specification is an engineering contract that lists all the goals Capacitor 10uf typical for a project: Provides additional filtering from main goals include area, power, throughput, latency, functionality, test

-- sequential behavior: always blocks-- pitfalls-- other useful features ... separate behavior from implementation. We need a Hardware Description Language ... known value or when the predicted value is an illegitimate logic value (e.g., due to contention on a tri-state bus). ...

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