Transcription of Introduction to CMOS VLSI Design - University of Notre Dame
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Introduction to CMOS VLSI Design - University of Notre Dame
1 Introduction toCMOS VLSID esignVLSI Design RulesPeter KoggeUniversity of Notre DameFall 2011, 2012, 2015, 2018 Based on material fromProf. Jay Brockman, Joesph Nahas, University of Notre DameProf. David Harris, Harvey Mudd vlsi DesignDesign RulesSlide 2 Outline Overview Determining Design Rules and Mask Biases Design Rules Circuit Interconnect Layout2 CMOS vlsi DesignDesign RulesSlide 3 layout Overview Minimum dimensions of mask features determine: transistor size and die size hence speed, cost, and power Historical Feature sizef= gate length (in nm) Set by minimum width of polysilicon Other minimum feature sizes tend to be 30 to 50% bigger.
2 Design Rules CMOS VLSI Design Slide 3 Layout Overview Minimum dimensions of mask features determine: – transistor size and die size – hence speed, cost, and power “Historical” Feature size f = gate length (in nm) – Set by minimum width of polysilicon – Other minimum feature sizes tend to be 30 to 50% bigger. Design or Layout Rules: rules ...
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