Transcription of Introduction to Verilog
{{id}} {{{paragraph}}}
Example: marketing
Introduction to Verilog
Introduction to VerilogOct/1/03 Peter M. Nyasulu, J Knight9 Table of Contents1. 12. 2 White Space, Comments, Numbers, Identifiers, Operators, Verilog Keywords3. Gate-Level 3 Basic Gates, buf, not Gates, Three-State Gates; bufif1, bufif0, notif1, notif04. DataTypes .. 4 Value Set, Wire, Reg, Input, Output, InoutInteger, Supply0, Supply1 Time, Parameter5. 6 Arithmetic Operators, Relational Operators, Bit-wise Operators, Logical OperatorsReduction Operators, Shift Operators, Concatenation Operator,Conditional Operator: ? Operator Precedence6. Operands .. 9 Literals, Wires, Regs, and Parameters, Bit-Selects x[3] and Part-Selects x[5:3] Function Calls7. 10 Module Declaration, Continuous Assignment, Module Instantiations,Parameterized Modules8. 12 Procedural Assignments, Delay in Assignment, Blocking and Nonblocking Assignmentsbegin.
Introduction to Verilog Oct/1/03 3 Peter M. Nyasulu and J Knight Primitive logic gates are part of the Verilog language. Two properties can be specified,drive_strengthand delay. Drive_strengthspecifies the strength at the gate outputs.The strongest output is a direct connection to a source, next
Loading..
Information
Domain:
Source:
Link to this page:
Please notify us if you found a problem with this document: